Has anyone seen this front-end before?

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Andre, hen I said 5% I meant current imbalance, not Vbe difference. IE 1mA/1.05mA. Same as hen I said 2.7mV Vbe difference gives a 10% current mismatch; 1mA/1.1mA. I'm sorry I asn't very clear on this. %Vbe ould indeed be a useless measure.

ere I to actually match pairs I ould do hat you describe. But I as measuring 10 at once. Again I do not think temperature ould selectively alter Vbe's to bring these transistors ithin 300uV of each other. I do not consider my measurements state of the art, but they certainly aren't insignificant. It as just a trial run to gain some perspective.
 
The only quartet I could get to work well without stability issues is using a diamond buffer driving a driver, driving output transistors, very much the same as you have shown on your webpage. I got the idea from pioneer that used this setup in early 1990s as outputstage in their top of range amp lineup. If youd like I can send you schematics although your outputstage is very much the same. The usual miller cap on the drivers and base resistors on the outputs are enough for stability.

Hi homemodder,

I show such a Diamond Buffer Quad (DBQ) in Figure 25.7 on page 516 in my book Designing Audio Power Amplifiers. It is a fairly simple and straightforward circuit. It is basically a Diamond buffer with bootstrapped collectors where the first emitter follower of a Locanthi T-circuit triple would be. There is of course a slight bit of added complexity in the form of the required current sources.

The nice thing about the DBQ is that the Vbe's of the diamond buffer cancel each other out in regard to thermal changes if the PNP and NPN transistors of the Diamond buffer are at about the same temperature (for example, 2SA1381 and 2SC3503 bolted together back-to-back). This arrangement will tend to be more thermally stable than a Triple, where a total of six Vbe are added up.

This circuit may also help give you back some of the Vbe of headroom you lost when you went from a double to a triple, depending on the saturation voltage of the current source you use.

Stability should not be a problem if modest base stopper resistors are used in front of the main driver and output transistors and the rails are well-decoupled and don't have a lot of stray inductance.

Cheers,
Bob
 
Harry probably meant by 'slow' the long turnoff time of a CFP BJT OPS.

Well, there is that. I was actually talking about small-signal bandwidth but it turns out I was wrong! :eek::(:confused::eek: This opinion was based on simulations I performed a long time ago; clearly I did something wrong or my models were flawed. I've just done some more simulations in LTspice using my and Bob's transistor models; I'm confident these are giving true-to-life predictions.

Yes, but I already clarified that my plan is NOT CFP output transistors.
It is the use of a CFP [pre-driver + driver] to drive an EF output.
As opposed to 2 cascaded EFs to drive the EF output.
Adequate bias means that effectively the CFP is class A so I don't see a problem.

Yes, I always knew you were talking about using a CFP as a driver, not as the final output. However, when using the CFP as a driver, there is no reason why it has to be biassed in class-A. Class of operation depends on the bias voltage and the value of the resistor joining the two halves' (+ve/-ve) outputs.

So here's the results of some simulations I've done. I've compared four different triples: two EF triples, one where the three stages operate in class-A, class-A and class-B and the other where the three stages operate in class-A, class-AB and class-B; and two [CFP+EF] triples, one where the CFP is class-A and the EF is class-B, and the other where the CFP is class-AB and the EF is class-B. Here is a pdf of the simulation schematic, the EF triples are up top and the [CFP+EF] triples are below. In both cases the more heavily biassed (in terms of current in the driver stages) configurations are on the left.

Here is a pdf of the small-signal analysis showing input impedance of the four configurations in the top pane, and frequency response in the bottom pane.

Finally, LTspice predictions for THD-20k, using a 4R load and 40 V peak output sinewave, and the first 10 harmonics for the calculations:

Class-A, class-A, class-B EF triple: 0.078 %
Class-A, class-AB, class-B EF triple: 0.081 %
Class-A, class-B [CFP+EF] triple: 0.068 %
Class-AB, class-B [CFP+EF] triple: 0.067 % (yes, lower than when the CFP stage is class-A biased; however please note that the voltage bias at the input of each configuration hasn't been precisely set to achieve exactly the same quiescent current in the final EF stage across all four configurations)
 
Excellent! thanks.

I was actually talking about small-signal bandwidth but it turns out I was wrong!

Nice to learn it wasn't just my failure to understand and nice to have cleaned up an error.

... when using the CFP as a driver, there is no reason why it has to be biassed in class-A. Class of operation depends on the bias voltage and the value of the resistor joining the two halves' (+ve/-ve) outputs.

I should have been more explicit earlier rather than just written "adequate".

So here's the results of some simulations I've done...

Finally, LTspice predictions for THD-20k, using a 4R load and 40 V peak output sinewave, and the first 10 harmonics for the calculations:

Class-A, class-A, class-B EF triple: 0.078 %
Class-A, class-AB, class-B EF triple: 0.081 %
Class-A, class-B [CFP+EF] triple: 0.068 %
Class-AB, class-B [CFP+EF] triple: 0.067 %. ..

Thank you for that. Trends are mostly as expected but excellent to have quantitative data.
There seems no point in the low bias versions, the hi bias EF3 is both faster AND flatter.
So it's hi bias versions - CFP+EF versus EF3.
The CFP is just a little lower open loop distortion but considerably more extended hi frequency response than EF3.
The extended CFP+EF response obviously offers the possibility of a faster feedback loop to lower the distortion even more but the peak is a bit of a worry. No wonder they have a reputation for stability problems!
It would be nice to actually exploit that peak, perhaps it is possible to use it to put in a Bode step. I will think about this, do you have any ideas or references for this?

Best wishes
David
 

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Hello Harry,

You could predict the results. The open loop output stage dominates THD.

Regards
Arthur
 

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Hello Harry,

You could predict the results. The open loop output stage dominates THD.

Regards
Arthur

Thanks Arthur. Sorry, should have been more clear: same test, but without the ideal buffer. I'm trying to get an idea of how much the input impedance of the simple output stage upsets the TIS front end.

Although now I think about it I'm wondering if that's a flawed test anyway. I'm still trying to get my head around why the THD is quite "high" for the complete amplifier as shown in your post #103. At first one might say that it's because the simple output stage doesn't have high enough or linear enough an input impedance so is upsetting the front end, but then you add the ideal buffer and the THD doesn't change. To me, this suggests that the TIS isn't being upset, there's just not enough loop gain to linearise the output stage.
 
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Had a few ideas too late to include in the previous post.

... or my models were flawed. I've just done some more simulations in LTspice using my and Bob's transistor models; I'm confident...

This seems a fine validation of the power of the feedback perspective. It did not need any detailed calculations to reveal what looked like, and was, an error.

... when using the CFP as a driver, there is no reason why it has to be biassed in class-A. Class of operation depends on the bias

The current in the driver is quite non-linear as the conduction switches from side to side. Self makes the point that it is not necessary to have the driver in Class A, only that it be "in conduction before the outputs turn on" and still on when the outputs turn off. I would include some time to stabilize. I think the extra current in the driver does not really place the driver in class A but that the lower resistor improves the turn-off of the output transistor. To have true class A the load resistor of the CFP would need to be connected to the opposite rail, EF type III in Self's notation.
The Spice AC analysis is linearized around the quiescent state so may not accurately model the non linearity of the conventional EF type II.
I would like to study this more, can you post your Spice ASC and models so I can replicate your results? Then we can share the monkey work!

Best wishes
David
 
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Thanks Arthur. Sorry, should have been more clear: same test, but without the ideal buffer. I'm trying to get an idea of how much the input impedance of the simple output stage upsets the TIS front end.

Although now I think about it I'm wondering if that's a flawed test anyway. I'm still trying to get my head around why the THD is quite "high" for the complete amplifier as shown in your post #103. At first one might say that it's because the simple output stage doesn't have high enough or linear enough an input impedance so is upsetting the front end, but then you add the ideal buffer and the THD doesn't change. To me, this suggests that the TIS isn't being upset, there's just not enough loop gain to linearise the output stage.

Hello Harry,

If you load the TIS output with a feedback network as it stands it loads the output of this stage too much causing much higher distortion than if there was a buffer there, put another way a buffer of some sort is needed to handle the lowish impedence of the feedback network.

Am I missing something in the way you want this sim setup.

Regards
Arthur
 
Hello Harry,

If you load the TIS output with a feedback network as it stands it loads the output of this stage too much causing much higher distortion than if there was a buffer there, put another way a buffer of some sort is needed to handle the lowish impedence of the feedback network.

Am I missing something in the way you want this sim setup.

Regards
Arthur

That's why I started wondering if the test was flawed. You could use an ideal buffer just to drive the feedback network; however you do it the feedback will reduce the TIS output impedance to make it more tolerant of loading.
 
I think the extra current in the driver does not really place the driver in class A but that the lower resistor improves the turn-off of the output transistor. To have true class A the load resistor of the CFP would need to be connected to the opposite rail, EF type III in Self's notation.

How are you defining "true" class-A? To me class-A in a push-pull stage means your standing current is at least half the output current so neither device (+ve/-ve) ever reaches a state of zero current (this definition excludes sliding bias from being class-A). That's the situation in my sims for stages I've described as being in class-A.

can you post your Spice ASC and models

.asc attached, models can be found from the post I linked earlier (I'm linking the post as it has useful background info) and Bob's site.
 

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The effect on TIS stage THD by input impedence of output stage

Hello Harry,

I put an ideal buffer between the Tis output and feed back network, and then unbuffered TIS driving open loop output stage (Red FFT is THD spectrum) , but I also added an additional ideal stage between the open loop output and TIS output as a reference point (Green FFT is this spectrum).

The plots clearly show how the input stage of the output affects the THD of the TIS stage.

Regards
Arthur
 

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................were I to actually match pairs I would do hat you describe. But I as measuring 10 at once. Again I do not think temperature would selectively alter Vbe's to bring these transistors within 300uV of each other. I do not consider my measurements state of the art, but they certainly aren't insignificant. It as just a trial run to gain some perspective.
with identical Collector load resistors and identical Vbe applied to all 10 DUTs, there is no guarantee that all 10 Tj are near the same. In "fact" they could be very different.
That's where your group method falls apart. It can only ever get you to "near enough" batching, ready for the next stage of more careful matching.
 
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Hi homemodder,

I show such a Diamond Buffer Quad (DBQ) in Figure 25.7 on page 516 in my book Designing Audio Power Amplifiers. It is a fairly simple and straightforward circuit. It is basically a Diamond buffer with bootstrapped collectors where the first emitter follower of a Locanthi T-circuit triple would be. There is of course a slight bit of added complexity in the form of the required current sources.

The nice thing about the DBQ is that the Vbe's of the diamond buffer cancel each other out in regard to thermal changes if the PNP and NPN transistors of the Diamond buffer are at about the same temperature (for example, 2SA1381 and 2SC3503 bolted together back-to-back). This arrangement will tend to be more thermally stable than a Triple, where a total of six Vbe are added up.

This circuit may also help give you back some of the Vbe of headroom you lost when you went from a double to a triple, depending on the saturation voltage of the current source you use.

Stability should not be a problem if modest base stopper resistors are used in front of the main driver and output transistors and the rails are well-decoupled and don't have a lot of stray inductance.

Cheers,
Bob

Bob I find the circuit in your book superior to a triple EF, the best advantage to me is stability from oscilation. The circuit Ive been using for a while now which is based on the pioneer from 20 years back goes one further and adds a driver after the four transistor diamond buffer. The diamond buffer also features bootstrapping just as shown in your book. The driver is composed of two transistors in parralell to achieve higher bandwith and lower device capacitances at optimal bias point. The input transistors of the DB are composed of darlington pairs providing very high bandwith and input impedance. The engineers at pioneer went all out to create a very high performance outputstage without reverting to error correction. This amp was a 20 000 $ beast regarded by many as this manufacturers best.
 
Bob I find the circuit in your book superior to a triple EF, the best advantage to me is stability from oscilation. The circuit Ive been using for a while now which is based on the pioneer from 20 years back goes one further and adds a driver after the four transistor diamond buffer. The diamond buffer also features bootstrapping just as shown in your book. The driver is composed of two transistors in parralell to achieve higher bandwith and lower device capacitances at optimal bias point. The input transistors of the DB are composed of darlington pairs providing very high bandwith and input impedance.

Please could you post a schematic image?
 
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