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Old 15th September 2012, 09:18 AM   #951
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Hi Harry,

>a 100 k resistor to ground, does this help to make the load on the front end look more linear?

At first glance I don't think so. Admittedly, the relative nonlinearity will be less, but it's the absolute value of the nonlinear load currents that counts. IOW, adding a linear load doesn't reduce the nonlinear load.

Cheers,
E.
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Old 15th September 2012, 11:06 AM   #952
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Quote:
Originally Posted by Edmond Stuart View Post
You will need at least a triplet...
Yes, I meant a triplet as the minimal OPS.
In particular I planned a CFP + EF triplet.
But a sim of a triple EF OPS was a bit of a disappointment so perhaps a triple is insufficient. So I want to sim a diamond buffer ahead of a CFP + EF. Could be called a quad or a buffered triple. Sorry if that was not clear.
My concern is because the simplicity of the super TIS is less attractive if there is a compensatory increase in the complexity of the OPS.
A Super TIS variant that tolerates low impedance sufficiently to work well with a triple OPS would be the best of both worlds. But not easy to find so far!

Best wishes
David
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Old 15th September 2012, 11:20 AM   #953
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David, what output transistors and models did you use for your sim? Presumably you get similar sim results as Edmond for the front-end stand alone. Any reason you wanted to use a CFP+EF triple rather than a diamond buffer + EF triple?
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Old 15th September 2012, 11:59 AM   #954
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Quote:
Originally Posted by HarryDymond View Post
David, what output transistors and models did you use for your sim? Presumably you get similar sim results as Edmond for the front-end stand alone. Any reason you wanted to use a CFP+EF triple rather than a diamond buffer + EF triple?
It was not my sim. Arthur did it back at post #103 and Edmond replied that it was consistent with his own results so I did not repeat it.
A CFP + EF looks to be a desirable for bias thermal stability. The EF can be thermal trak with excellent speed and accuracy of bias stability. The driver bias variation is servo-ed out by the CFP and the pre-driver has very little variation in power dissipation and is a TO-126 that can be easily bolted to another TO-126 for ambient correction. Also there is a theoretical benefit to use a CFP (that is a small loop) rather than 2 cascaded loops (to consider the EF as a little -ve feedback loop). A simple form of nested loops in other words.

Best wishes and off to bed for me now
David
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Old 15th September 2012, 12:59 PM   #955
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Originally Posted by Dave Zan View Post
It was not my sim. Arthur did it back at post #103 and Edmond replied that it was consistent with his own results so I did not repeat it.
Ah, ok. What I see in that post is what I meant by a diamond buffer + EF triple (as what I mean is [diamond buffer + EF] triple, rather than [diamond buffer] + [EF triple]). Arthur, where did your transistor models come from? Many are really poor. If the models for the drivers aren't great, how about trying my 2SC5171/2SA1930 models? And for the final output devices, I wonder if using 1302/3281 output transistors would make much difference as these have flatter beta vs. Ic, and higher Vceo with possibly correspondingly lower early effect (although this doesn't always go hand-in-hand).

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Originally Posted by Dave Zan View Post
Also there is a theoretical benefit to use a CFP (that is a small loop) rather than 2 cascaded loops (to consider the EF as a little -ve feedback loop).
I don't really like CFPs. I've never made one that didn't suffer parasitic oscillation under some conditions (although this was a very long time ago and possibly things I've learnt since then in terms of layout etc. would help here), they are slow (excess phase kicks in at much lower frequency than with an EF) and whilst there is the tight negative feedback loop, this linearises each half (+ve/-ve) separately and you still have issues with crossover distortion; the crossover is very "sharp" and produces lots of high-order harmonics. Really I'd only consider a CFP operating in class-A and I don't like the corresponding quiescent power dissipation.
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Old 15th September 2012, 03:22 PM   #956
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or, a CFP running in ClassA, followed by an EF.
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Old 15th September 2012, 03:25 PM   #957
dadod is online now dadod  Croatia
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Default PCB Layout

Maybe here some of skilled layout designers could take a challenge and suggest good layout for this amp: TT amp, 200W/8ohm, 701W/2ohm according ongoing discurion.
Damir
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Old 15th September 2012, 11:06 PM   #958
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Ho much matching do you think is necessary for this frontend? I just measured 10 Fairchild BC550C's. They ere mostly ithin .3mV of each other, but never larger than .8mV apart. In the simulator I find a 2.7mV mismatch causes a 10% current difference in an LTP and a .3mV difference causes a 1.1% current difference.

hich is more important for 2nd harmonic cancellation, matched Ic or matched Vbe? For instance, is Gm dependent on Ic and independent of Vbe? Or, if I have Vbe mismatched transistors, can I intentionally mismatch Ic in order to match Gm and cancel the 2nd harmonic? The simulator is telling me even different transistors ill cancel if just the Ic is kept matched. So I'm guessing Gm is dependent on Ic and independent of Vbe. So for input stages, it seems matching is not as useful if you're not using a (matched) current mirror. And it is seeming that Ic matching has to be ithin 6uA to loer the 2nd harmonic belo the 3rd. This ould seem to require better matching than .3mV, hich ill be somehat tedious...
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Old 16th September 2012, 12:35 AM   #959
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Quote:
Originally Posted by HarryDymond View Post
Ah, ok. What I see in that post is what I meant by a diamond buffer + EF triple (as what I mean is [diamond buffer + EF] triple, rather than [diamond buffer] + [EF triple])
I worked out what you meant. I would call that "a diamond buffer EF triple" as opposed to a "diamond buffer + EF triple" but I like your new notation. Would have saved the uncertainty between Edmond and myself.

Quote:
I don't really like CFPs. I've never made one that didn't suffer parasitic oscillation under some conditions (although this was a very long time ago and possibly things I've learnt since then in terms of layout etc. would help here), they are slow (excess phase kicks in at much lower frequency than with an EF) and whilst there is the tight negative feedback loop, this linearises each half (+ve/-ve) separately and you still have issues with crossover distortion; the crossover is very "sharp" and produces lots of high-order harmonics. Really I'd only consider a CFP operating in class-A and I don't like the corresponding quiescent power dissipation.
Yes, completely concur that the linearization of each half separately and resultant sharp crossover makes the CFP undesirable as an output.
But as a pre-driver + driver to an EF then the CFP is effectively in class A so the linearization is a benefit. And there is a minor improvement in headroom and efficiency from less volt drop as well as the previously mentioned thermal stability benefit.
So it seems to retain the best points of a CFP that D. Self touts and avoid all the problems that Bob Cordell cautions.
Well, perhaps not all the problems. I am concerned about parasitic oscillations, of course. I have seen many trial and error recommendations but little analysis and optimization. Do you have any analyses that you can recommend?
You say "they are slow". Not sure I follow. If we consider this as a feedback problem then I think we should be able to do better or at least as well as two separate loops. Can we use TMC in a CFP? I already satisfy Self, Cordell and AndrewT and now Edmond will like it too

Best wishes
David

Last edited by Dave Zan; 16th September 2012 at 12:44 AM.
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Old 16th September 2012, 01:38 AM   #960
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Dave, in my high-current K-multipliers I have had success ith shunt compensation. An L/R could probably be used helpfully but I did not ant to radiate. The idea is to use degeneration to limit Gm hen current is high, so that the Ft's of the transistors are more consistent and thus more responsive to hichever compensation you choose. Bummer, I kno. But it orks best out of anything I have tried in simulation, and is also still nicely fast.

Because of the high currents involved, usually large film capacitors ould be needed to stabilize a CFP any other ay, and these ould ruin distortion, sitching behavior, input impedance, speed and so on. L/R combos might be more useful but again there is the radiation issue.

Upper pair curves are output impedance, loer curves are line rejection. Another important thing about this compensation is that it has minimal impact on line rejection.

It is important to note that the CFP output stage has a "distended" tempco. This is because the Vbe and Hfe tempco of the outputs is mirrored in the Vbe of the drivers, in addition to their tempco. If e define tempco in "diode" units, e find that this gives us a fractional tempco, hich means thermal compensation may be very difficult to achieve ithout over or under compensating. This is problematic because e certainly don't ant thermal runaay and e also don't ant our bias to creep don and cause nasty sitching. There be beasts in the ater.
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