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Old 30th March 2012, 06:35 PM   #61
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Quote:
Originally Posted by Edmond Stuart View Post
To all,

Regarding the circuit as shown below, I like to know whether anyone has seen this front-end before. If so, I'm curious to learn more about it and how it behaves in real life. More details can be found here.
(BTW, I'm still editing and updating that page, so it's not yet finished)

Cheers,
E.
Hi Edmond,

This is an interesting and clever circuit.

However, R12 and R14 straddle the power supply rails and I believe they will introduce power supply noise and degrade PSRR. Did I get this right?

Cheers,
Bob
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Old 30th March 2012, 07:08 PM   #62
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each 100k R is cross coupled to the input side of each opposing current mirror - should give very good cancellation for ps diff V - if the signs work out??? - not certain now that I think more about it

I would just use one 100k bias R and then the while the VAS bias current is slightly modulated there is little conversion to output current


haven't yet set up a Ltspice sim - I expect best performance would had with error corrected/local feedback output stage giving high input Z, gain close to 1

will be interesting to see stability with all of the nested feedback around the output Q


it would be helpful if Kean posted the .asc

Last edited by jcx; 30th March 2012 at 07:27 PM.
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Old 30th March 2012, 09:54 PM   #63
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You were right, it's at 20MHz not 100MHz. Erm...

The output stage could be one of my Allison variations, they can have extremely high input impedance. Could also be geometric mean class A.

Ed, I think a better way is to feed the cascodes from the outputs of the current mirrors. This increased PSRR in my simulations.

It seems that any attempt to improve common mode PSRR degrades differential PSRR and vice-versa. Relying on ripple-induced currents to cancel is not the best option I think, if it can be helped.
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Old 31st March 2012, 09:51 AM   #64
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Quote:
Originally Posted by Edmond Stuart View Post
Hi Stein,

With your NXP models, the test circuit (from post 44) still peaks at about 15MHz.
(that is, if C1=C2=C3=0)

edit: With a light capacitive load on the output (as in real life) everything looks fine.

Cheers,
E.
Hi Edmond

That's strange, maybe you should try to bypass the LED's with small C's.

BTW: what is the model you are using for the IRLED's

Cheers
Stein
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Old 31st March 2012, 11:15 AM   #65
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Default Straddle

Quote:
Originally Posted by Bob Cordell View Post
Hi Edmond,

This is an interesting and clever circuit.

However, R12 and R14 straddle the power supply rails and I believe they will introduce power supply noise and degrade PSRR. Did I get this right?

Cheers,
Bob
Hi Bob,

As JSX already pointed out, power supply noise is canceled. Nevertheless, your worry about the PSRR impels me to have a closer look at this matter. Thanks! It appears that rearranging these two R's results in an even better PSRR. See my updated website Fig.1, R12 & R14 and Fig.2, R21 & R22.

Cheers,
E.
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Old 31st March 2012, 11:39 AM   #66
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Quote:
Originally Posted by jcx View Post
each 100k R is cross coupled to the input side of each opposing current mirror - should give very good cancellation for ps diff V

Quote:
- if the signs work out??? - not certain now that I think more about it

I would just use one 100k bias R and then the while the VAS bias current is slightly modulated there is little conversion to output current
I prefer a constant TIS current, independent of the supply voltage. It cost only one extra R.
Skimping on one resistor would be the ultimate example of false economy.

Quote:
haven't yet set up a Ltspice sim - I expect best performance would had with error corrected/local feedback output stage giving high input Z, gain close to 1
Exactly!

As a matter of fact, this TIS is designed having this OPS in mind.

Cheers,
E.
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Old 31st March 2012, 11:41 AM   #67
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Originally Posted by stinius View Post
Hi Edmond
That's strange, maybe you should try to bypass the LED's with small C's.
BTW: what is the model you are using for the IRLED's
Cheers
Stein
Hi Stein,

I'm using this model (home brew):
.MODEL irled D (BV=5 EG=1.7 IS=1e-23 RS=5)

Cheers,
E.
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Old 31st March 2012, 11:51 AM   #68
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Quote:
Originally Posted by keantoken View Post
[...]
Ed, I think a better way is to feed the cascodes from the outputs of the current mirrors. This increased PSRR in my simulations.
Hi Keane,

Nope. RC bootstrapping gives the lowest distortion and doesn't degrade the PSRR.

Quote:
It seems that any attempt to improve common mode PSRR degrades differential PSRR and vice-versa. Relying on ripple-induced currents to cancel is not the best option I think, if it can be helped.
The PSRR has been further improved and THD is even slightly lower, see the new fig.1 on my website.

Cheers,
E.
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Old 31st March 2012, 12:58 PM   #69
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Originally Posted by keantoken View Post
I would like to be called Keane. My wishful thinking is that my accomplishments will be known under that name...

I would be flattered to build your frontend too, unfortunately my bench is not that great (yet) and I'm of limited means. My soldering iron tip has corroded again, and who knows when I'll be able to get another one.

Adding a diode to the emitter of Q10 and Q11 would get the Baxandall drivers out of danger of quasi-saturation, but I don't know if this would bring any benefits to the circuit. Maybe better PSRR. Using a Widlar or other suitable current mirror to increase the Vce of the current mirrors may bring an improvement in current balance for the same reason.

I only started understanding most of this stuff in an organized way this year, and I've just graduated from HS, so be advised...

I found your capacitor trick to be entirely ineffective at curing oscillation in simulation, and it caused problems of it's own. This cascode has VERY specific needs. Specs are not as great after compensation, but this is a necessity.

Attached is what I came up with to stabilize the Baxandall cascode. This gets it stable, and with more extreme values it can be made unconditionally stable. I don't know if it can be stable any other way. The simulator suggests it has stability as-is, but I doubt it works like that in real life. Unfortunately this causes signal loss through the bias generator, but it's not too much at audio frequencies.

The diode is included to get the Baxandall driver out of quasi-saturation. Leakage between the base and collector (Early, w/e) decreases max output impedance (we control this specifically with the 47k resistor, which helps stability), so quasi-saturation is good to avoid. I'm not sure but I think it's necessary in real life. The 47k resistor is placed so there is no DC bias across it. May not matter, but why not?

Increasing the 1k resistor decreases the effectiveness of the cascode since it sort of degenerates the driver through the base. 1k was a good compromise, as far as cascode performance, but increasing it decreases signal loss through it and that may be more important.

If no one else has stabilized the Baxandall, let it be known that I was first!!!


THD20 is .000002% at 1V output.
Hello Kean

With your simulations you say TH20 is 0.000002% at 1V output is the THD measured at a frequency of 20 Hz and is 1V output meant to be at the input level of the amp stage. I am just a bit confused

Regards
Arthur
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Old 31st March 2012, 08:17 PM   #70
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I meant THD @20KHz at +-1V at the output.

I considered building this circuit yesterday, as I have several BC847DPN, which are dual npn/pnp pairs with "good Hfe matching". Unfortunately I don't have any same-polarity pairs I could use for the current mirrors or LTPs.

I will test the latest improvements in simulation... Good work Edmond.
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