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Old 29th March 2012, 02:22 PM   #51
dadod is offline dadod  Croatia
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Quote:
Originally Posted by Edmond Stuart View Post
Hi Dado,

Congratulations! For an amp of limited complexity, that is an extreme good figure.
BTW, did you check the phase margin of the internal Miller loop as well as the global NFB loop?

Cheers,
E.
Here are two feedback loop gain plots. First one with TMC resistor connected after the probe, and second one is with TMC resistor connected to the output. I tried before to simulate the internal Miller loop but with very strange result and I think I am doing it wrongly.
cheers dado
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File Type: jpg TT-EF-loopgain.jpg (231.5 KB, 410 views)
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Old 29th March 2012, 02:36 PM   #52
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Hi Damir,

That looks okay. As for the Miller loop, keep trying. It's important to ensure/verify it has enough phase margin.

Cheers,
E.
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Old 29th March 2012, 02:52 PM   #53
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Hi Edmond
As others are saying, it's an interesting circuit, I tried something similar one or two years ago (not the same IPS and CM, but the TIS, and a TIS also with a bootstrapped super pair) I got the same peaking around 19MHz and was unable to fix it without a big drop in performance, so I gave up the whole idea. And forgot the circuit until I saw your circuit.
Your idea, by using C1 and C2 (in the TIS test setup) seems to fix the problem.

BTW: I tried something else today, try to use the attached models for Q7 and Q8 in the TIS test, these are NXP advanced models (better quasi sat. models). see attached picture (without C1 and C2).

BTW 2: I have been busy with other things the last months, but have finished the amp I emailed you some months ago, rock stable.

Cheers
Stein
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File Type: jpg ES-TIS-Test.jpg (57.8 KB, 404 views)
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File Type: txt BCM847DS.txt (876 Bytes, 26 views)
File Type: txt BCM857DS.txt (1.8 KB, 18 views)
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Old 29th March 2012, 04:41 PM   #54
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Quote:
Originally Posted by stinius View Post
Hi Edmond
As others are saying, it's an interesting circuit, I tried something similar one or two years ago (not the same IPS and CM, but the TIS, and a TIS also with a bootstrapped super pair) I got the same peaking around 19MHz and was unable to fix it without a big drop in performance, so I gave up the whole idea. And forgot the circuit until I saw your circuit. Your idea, by using C1 and C2 (in the TIS test setup) seems to fix the problem.
Hi Stein,

Indeed, seems to fix the problem. However, Keane has still troubles with it.

Quote:
BTW: I tried something else today, try to use the attached models for Q7 and Q8 in the TIS test, these are NXP advanced models (better quasi sat. models).
Thanks for the models, though one question: the additional components in the PNP model seems to be missing in the NPN model. Is this correct?

Quote:
see attached picture (without C1 and C2).
Is this picture from my test setup up or a different one?

Quote:
BTW 2: I have been busy with other things the last months, but have finished the amp I emailed you some months ago, rock stable.

Cheers
Stein
I suppose you mean the amp with the H-bridge input stage and diamond driver, right?
Glad to hear it's working so well.

Cheers,
E.

PS: Any news from 'overthere'?
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Old 29th March 2012, 06:17 PM   #55
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Hi Edmond

Has Kean told you what kind of troubles he has with the C solution?

It's quite easy to see the results if you run an AC analysis and stepping the C's.
Depending on the rest of the circuit you will find an optimum value for the C's

I'm using factory models for all the transistors, I guess Kean is using Bob's (better)models.

I don't know why NXP don't include the extra components in both models.

The picture in my previous post are from your test setup, see attached picture of the setup I'm using.

Yes it's the H bridge with the "Diamond" ops. ( if the contest is to use as few tranistors as possible, I'm a looser).

No, no news from over there.

Cheers
Stein
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Old 29th March 2012, 07:15 PM   #56
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Quote:
Originally Posted by Edmond Stuart View Post
Hi Keane,

To a certain extent I share your concern about quasi saturation (I wish I had better models). On the other hand, I've seen many circuits with transistors operating at Vce ~= 0.6V. But if it works, I prefer it this way, as one of objectives was a near rail to rail output swing. This is because I hate using an elevated and/or separate PSU for the front-end.



Other people have reported instabilities as well, but I haven't encountered them yet. Dimitri Danyuk has built similar circuits (see his AES paper), but no mention about instability (BTW, the Baxandall transistors in his circuit operate at 0.6V). I have also simmed the circuit with other transistor models (2N5401, 2N5551, 2SA1407 & 2SC3601) but no sign of instability. So what's going on? Has it something to do with the spice models?

As for the capacitor trick (470pF), these caps do have an effect according the test circuit as shown below, fig.1.
Fig. 2: C1 = C2 = C3 = 0. It peaks at 19MHz.
Fig. 3: C1 = C2 = 470pF, C3 = 0
Fig. 4: C1 = C2 = 0, C3 = 10pF
As you see, no sign of instability with either of these caps.

Anyhow, can you give me the models of your transistors (in spice format, no LT format, please)? Maybe it will provide a clue.

BTW, the 100k bias resistors are wrong connected (not a fatal error, I think).

Cheers,
E.
I use Bob Cordell's models, from here. I thought LTSpice was compatible with normal SPICE.

CordellAudio.com - SPICE Models

It is believable that there would not be stability problems at low Vce, if the BC junction had more leakage than the 47k resistors in my schematic. As I recall a normal BJT CCS can have 100k impedance just from C-B leakage, regardless of the emitter current feedback loop. The cascodes may not be operating in full capacity. SPICE may also be pessimistic. I found it was unstable, but would not oscillate, with 100k resistors which is why I increased them to 22k, so I could look at how to stabilize the circuit. Another reason to increase these resistors is to have higher slew rate.

In looking for instability you are looking in the wrong place. It will not occur as a kind of peaking in response. It is internal to the cascode current loop and occurs at much higher frequencies; to me it appears as a resonance or extreme phase shift around 100MHZ. It is easiest to observe if you hang a 1F cap to ground from the feedback point so the TIS operates open-loop at high frequencies. It is a kind of parasitic instability, but it grows until it throws the cascode into repeated saturation. If uncompensated, you may get away with it but the peaking will probably still be there, and the circuit may have anomalous problems.

Now I must read the new replies...
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Old 29th March 2012, 07:26 PM   #57
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By "undonditionally stable" I mean it will be stable with any impedance load. Many circuits are stable without peaking normally but will oscillate into certain reactive loads.

The Baxandall cascodes seem to like to oscillate with 10u inductors at their output. A feedback loop can emulate inductances, and for this reason the cascode may not behave like a normal common-emitter circuit.

Last edited by keantoken; 29th March 2012 at 07:28 PM.
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Old 30th March 2012, 12:19 PM   #58
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Quote:
Originally Posted by keantoken View Post
I
[snip]
If no one else has stabilized the Baxandall, let it be known that I was first!!!

THD20 is .000002% at 1V output. [E: i.e. 0.02ppm]
Hi Keane,

With your circuit I get 0.06ppm, BUT if Vcc=50V and Vo=40V then THD20k=5.8ppm.
So, this doesn't work, sorry.

Cheers,
E.
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Old 30th March 2012, 12:33 PM   #59
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Default Internal affair

Quote:
Originally Posted by keantoken View Post
[...]
In looking for instability you are looking in the wrong place. It will not occur as a kind of peaking in response. It is internal to the cascode current loop and occurs at much higher frequencies; to me it appears as a resonance or extreme phase shift around 100MHZ.
[...]
Hi Keane,

So it's an 'internal affair'. Therefore I've put a Tian gain probe at one of the Baxandall loops (circuit of post 44). Without any caps the phase/gain response is indeed problematic, on the verge of instability, but again at 19MHz, not 100MHz.
With a tiny cap at the output (10pF or so) the loop is stable (a gain margin of about 12dB).

Cheers,
E.
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Old 30th March 2012, 12:37 PM   #60
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Hi Stein,

With your NXP models, the test circuit (from post 44) still peaks at about 15MHz.
(that is, if C1=C2=C3=0)

edit: With a light capacitive load on the output (as in real life) everything looks fine.

Cheers,
E.
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Last edited by Edmond Stuart; 30th March 2012 at 12:40 PM.
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