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Old 30th June 2012, 09:31 AM   #551
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Quote:
Originally Posted by Dave Zan View Post
Seems that you and Jan have not been able to make them understand over in that thread!
Indeed, that was a rather frustrating experience: explaining something "pour les couilles du pape".
BTW, is there anybody who can translate this French saying? Perhaps Jan? (hint, in Dutch we say: 'voor de kat z'n kut')

Quote:
While there I saw the thumbnail of your current SuperTIS and I noticed there is not a TPC load on the super-pair, as recommended in Fig. 6 on your website. Any particular reason or you just decided to keep the circuit "simple"
Best wishes
David
It was a matter of trade-offs between phase margin of the Miller loop and distortion and finally I decided to let stability prevail.
In addition, I've changed the frequency compensation of the OPS to a 2nd order thingy.
Now, THD20k is below 1ppm, at least, according my sim.

Cheers,
E.
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Old 30th June 2012, 10:25 AM   #552
wahab is offline wahab  Algeria
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Quote:
Originally Posted by Edmond Stuart View Post
Indeed, that was a rather frustrating experience: explaining something "pour les couilles du pape".
BTW, is there anybody who can translate this French saying? Perhaps Jan? (hint, in Dutch we say: 'voor de kat z'n kut')
Litteraly , for (the sake of ) the pope s balls....

On another side , i checked Hitachi s laterals modeling.

It is indeed a power law that is used as approximation ,
the subthreshold is not modeled , BUT , below threshold
there s simply no conduction , so the model will undoubtly
yield more distorsion than in real world , particularly for
higher ranges harmonics.
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Old 30th June 2012, 10:32 AM   #553
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So even the strongest feedback loop can be unconditionally unstable unless you fool it somehow. If Tf is a time delay phenomenon, no amount of compensation can overcome this.

Sometimes I wonder why many designers go for the biggest, slowest outputs rather than paralleling smaller faster ones. The only benefit I can see is space and maybe total device capacitance. These devices are slower, and compensation can't overcome this (not easily anyways). Smaller outputs with higher Ft will not get any slower when paralleling, so you end up with more stability at higher bandwidth. For instance a pair of the MT-100 2SC3284 has better linearity, more speed, and more dissipation than the MT-200 2SC2922, and fits in the same space. Maybe total capacitance will be higher, but this can be compensated for. Maybe component count is another drawback; but it is in return for better performance.

I think the importance of Cbc in EF stages may be overrated. Cbe is a much ignored parameter that often makes all the difference. Most discrete devices, running at ordinary operating points are in the Ft region dominated by the Cbe-transconductance time constant. For outputs this is especially important. Sanken has nice LAPT transistors with Ft of 50MHz at several amps, but Ft at 100mA, where the majority of amps are biased, is lower than 20MHz. What good is the increased Ft at high currents if the Ft at crossover currents is mediocre? Outputs with >20MHz Ft at 100mA, with not much rise in Ft over the current range may actually be more useful for audio because the GBWP is not moving so much, and anomalous oscillation at power extremes is less likely.

For these reasons I choose outputs based on low-current Ft. I try to find outputs with Ft over 20MHz at 100mA. The 2SC2837/A1186 are a good candidate for paralleled fast output stages, although by the datasheets they will appear to give less linearity than the C3284/A1303. I previously thought Japanese semiconductors were best in this category, but looking through the MJLx281/x302 datasheets, it seems they are actually the best available. I learned OnSemi has acquired Sanyo, so maybe this explains it.

Am I on the right track? BTW I'm not confusing delay and phase, though maybe I mix terms a bit.
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Old 30th June 2012, 10:46 AM   #554
wahab is offline wahab  Algeria
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Good points , Kean..

Ft being lower at lower current is inherently a property of the BJts
since it s gm dependant , although not directly proportionnal as it
should normaly be , as measured by a specialist that is no more
hanging by there...
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Old 30th June 2012, 10:58 AM   #555
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Quote:
Originally Posted by keantoken View Post
So even the strongest feedback loop can be unconditionally unstable [snip].
Yes. In fact, the stronger the feedback, the more difficult to keep it stable. If you have an unstable amplifier you can almost always make it stable by decreasing the feedback (higher closed loop gain).
If you look at the data sheet for example for the LM3886 you will see a MINIMUM closed loop gain for stability - stronger feedback (lower closed loop gain) will make it unstable.

jan
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Old 30th June 2012, 11:47 AM   #556
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Well in my head it was a bit unclear what a "strong" feedback loop was, and that was not the concept I was focusing on anyways. My thoughts were as simple as: phase shift can always be corrected; delay cannot; therefore a feedback loop "strong" enough to correct any amount of phase shift would still be unconditionally unstable if a time delay were introduced.

Another point on Ft is that transistors with high Ft at low currents evidently have low Cbe, and this means there is less hullabaloo trying to move charge in and out of the base during switching. So switching behavior will be better with fast signals, and the bias will not be so badly affected by parasitic oscillation.

Incidentally I just blew up a prototype local feedback output stage. It has the current gain of a triple EF, but without the voltage distortion. High order distortions are reduced by a lot. It worked as predicted while it was running, but I couldn't tell whether the bias drift was due to rail sensitivity or bad thermal compensation. One aspect of this circuit is that it has indefinite and very fast drive capability - it destroyed the outputs before they had the opportunity to smoke. I clamped the heat sensing diodes under the collector pins, and now I suspect this kept the outputs from mating with the heatsink properly. I don't want to post any schematic until I've fully explored it, but I thought it was notable because it behaved the way I expected it would, concerning stability. But this time I will add the protection circuit. It is exciting to take solutions discovered in simulation and apply them to real circuits, when one is finally able to do this.
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Old 30th June 2012, 11:58 AM   #557
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Quote:
Originally Posted by wahab View Post
It is indeed a power law that is used as approximation ,
the subthreshold is not modeled , BUT , below threshold
there s simply no conduction , so the model will undoubtly
yield more distorsion than in real world , particularly for
higher ranges harmonics.
Incorrect. The absence of subthreshold conduction model will not make the distortion higher but lower. Due to the exponential Id-Vgs conduction law in the subthreshold region, the gm doubling distortion mechanism occurs, like in bipolars (with more high order harmonics, etc...). Otherwise, with only a power conduction law, the gm doubling distortion mechanism contribution is small.

This is again basic textbook stuff and applies to any mosfet type (not only laterals). If you want more proof, get the 2SK1530/2SJ201 level 1 and level 4 (developed by Andy_C) models and check it out for yourself.
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Old 30th June 2012, 12:25 PM   #558
wahab is offline wahab  Algeria
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Quote:
Originally Posted by Waly View Post
Due to the exponential Id-Vgs conduction law in the subthreshold region

Better an exponential variation at sub threshold than an abrupt
threshold wich will yield obviously way more high order switching
distorsion....
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Old 30th June 2012, 01:31 PM   #559
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Exactly, (and I have it checked out with models developed by Andy AND me).
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Old 30th June 2012, 02:02 PM   #560
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>This is again basic textbook stuff
Clearly, your textbook is a bit too 'basic'.
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