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Old 18th September 2012, 07:42 AM   #991
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Quote:
Originally Posted by PHEONIX View Post
Hello Harry,

You could predict the results. The open loop output stage dominates THD.

Regards
Arthur
Thanks Arthur. Sorry, should have been more clear: same test, but without the ideal buffer. I'm trying to get an idea of how much the input impedance of the simple output stage upsets the TIS front end.

Although now I think about it I'm wondering if that's a flawed test anyway. I'm still trying to get my head around why the THD is quite "high" for the complete amplifier as shown in your post #103. At first one might say that it's because the simple output stage doesn't have high enough or linear enough an input impedance so is upsetting the front end, but then you add the ideal buffer and the THD doesn't change. To me, this suggests that the TIS isn't being upset, there's just not enough loop gain to linearise the output stage.

Last edited by HarryDymond; 18th September 2012 at 07:53 AM.
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Old 18th September 2012, 08:13 AM   #992
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Had a few ideas too late to include in the previous post.

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Originally Posted by HarryDymond View Post
... or my models were flawed. I've just done some more simulations in LTspice using my and Bob's transistor models; I'm confident...
This seems a fine validation of the power of the feedback perspective. It did not need any detailed calculations to reveal what looked like, and was, an error.

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... when using the CFP as a driver, there is no reason why it has to be biassed in class-A. Class of operation depends on the bias
The current in the driver is quite non-linear as the conduction switches from side to side. Self makes the point that it is not necessary to have the driver in Class A, only that it be "in conduction before the outputs turn on" and still on when the outputs turn off. I would include some time to stabilize. I think the extra current in the driver does not really place the driver in class A but that the lower resistor improves the turn-off of the output transistor. To have true class A the load resistor of the CFP would need to be connected to the opposite rail, EF type III in Self's notation.
The Spice AC analysis is linearized around the quiescent state so may not accurately model the non linearity of the conventional EF type II.
I would like to study this more, can you post your Spice ASC and models so I can replicate your results? Then we can share the monkey work!

Best wishes
David

Last edited by Dave Zan; 18th September 2012 at 08:19 AM.
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Old 18th September 2012, 08:24 AM   #993
PHEONIX is offline PHEONIX  Australia
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Quote:
Originally Posted by HarryDymond View Post
Thanks Arthur. Sorry, should have been more clear: same test, but without the ideal buffer. I'm trying to get an idea of how much the input impedance of the simple output stage upsets the TIS front end.

Although now I think about it I'm wondering if that's a flawed test anyway. I'm still trying to get my head around why the THD is quite "high" for the complete amplifier as shown in your post #103. At first one might say that it's because the simple output stage doesn't have high enough or linear enough an input impedance so is upsetting the front end, but then you add the ideal buffer and the THD doesn't change. To me, this suggests that the TIS isn't being upset, there's just not enough loop gain to linearise the output stage.
Hello Harry,

If you load the TIS output with a feedback network as it stands it loads the output of this stage too much causing much higher distortion than if there was a buffer there, put another way a buffer of some sort is needed to handle the lowish impedence of the feedback network.

Am I missing something in the way you want this sim setup.

Regards
Arthur
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Old 18th September 2012, 08:26 AM   #994
dadod is online now dadod  Croatia
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What do you think about this OPS?

dado
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Old 18th September 2012, 08:36 AM   #995
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Originally Posted by PHEONIX View Post
Hello Harry,

If you load the TIS output with a feedback network as it stands it loads the output of this stage too much causing much higher distortion than if there was a buffer there, put another way a buffer of some sort is needed to handle the lowish impedence of the feedback network.

Am I missing something in the way you want this sim setup.

Regards
Arthur
That's why I started wondering if the test was flawed. You could use an ideal buffer just to drive the feedback network; however you do it the feedback will reduce the TIS output impedance to make it more tolerant of loading.
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Old 18th September 2012, 08:48 AM   #996
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Originally Posted by Dave Zan View Post
I think the extra current in the driver does not really place the driver in class A but that the lower resistor improves the turn-off of the output transistor. To have true class A the load resistor of the CFP would need to be connected to the opposite rail, EF type III in Self's notation.
How are you defining "true" class-A? To me class-A in a push-pull stage means your standing current is at least half the output current so neither device (+ve/-ve) ever reaches a state of zero current (this definition excludes sliding bias from being class-A). That's the situation in my sims for stages I've described as being in class-A.

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Originally Posted by Dave Zan View Post
can you post your Spice ASC and models
.asc attached, models can be found from the post I linked earlier (I'm linking the post as it has useful background info) and Bob's site.
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Last edited by HarryDymond; 18th September 2012 at 08:50 AM.
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Old 18th September 2012, 09:42 AM   #997
PHEONIX is offline PHEONIX  Australia
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Default The effect on TIS stage THD by input impedence of output stage

Hello Harry,

I put an ideal buffer between the Tis output and feed back network, and then unbuffered TIS driving open loop output stage (Red FFT is THD spectrum) , but I also added an additional ideal stage between the open loop output and TIS output as a reference point (Green FFT is this spectrum).

The plots clearly show how the input stage of the output affects the THD of the TIS stage.

Regards
Arthur
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Old 18th September 2012, 09:51 AM   #998
AndrewT is offline AndrewT  Scotland
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Originally Posted by keantoken View Post
................were I to actually match pairs I would do hat you describe. But I as measuring 10 at once. Again I do not think temperature would selectively alter Vbe's to bring these transistors within 300uV of each other. I do not consider my measurements state of the art, but they certainly aren't insignificant. It as just a trial run to gain some perspective.
with identical Collector load resistors and identical Vbe applied to all 10 DUTs, there is no guarantee that all 10 Tj are near the same. In "fact" they could be very different.
That's where your group method falls apart. It can only ever get you to "near enough" batching, ready for the next stage of more careful matching.
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Last edited by AndrewT; 18th September 2012 at 09:58 AM.
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Old 18th September 2012, 10:25 AM   #999
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Originally Posted by Bob Cordell View Post
Hi homemodder,

I show such a Diamond Buffer Quad (DBQ) in Figure 25.7 on page 516 in my book Designing Audio Power Amplifiers. It is a fairly simple and straightforward circuit. It is basically a Diamond buffer with bootstrapped collectors where the first emitter follower of a Locanthi T-circuit triple would be. There is of course a slight bit of added complexity in the form of the required current sources.

The nice thing about the DBQ is that the Vbe's of the diamond buffer cancel each other out in regard to thermal changes if the PNP and NPN transistors of the Diamond buffer are at about the same temperature (for example, 2SA1381 and 2SC3503 bolted together back-to-back). This arrangement will tend to be more thermally stable than a Triple, where a total of six Vbe are added up.

This circuit may also help give you back some of the Vbe of headroom you lost when you went from a double to a triple, depending on the saturation voltage of the current source you use.

Stability should not be a problem if modest base stopper resistors are used in front of the main driver and output transistors and the rails are well-decoupled and don't have a lot of stray inductance.

Cheers,
Bob
Bob I find the circuit in your book superior to a triple EF, the best advantage to me is stability from oscilation. The circuit Ive been using for a while now which is based on the pioneer from 20 years back goes one further and adds a driver after the four transistor diamond buffer. The diamond buffer also features bootstrapping just as shown in your book. The driver is composed of two transistors in parralell to achieve higher bandwith and lower device capacitances at optimal bias point. The input transistors of the DB are composed of darlington pairs providing very high bandwith and input impedance. The engineers at pioneer went all out to create a very high performance outputstage without reverting to error correction. This amp was a 20 000 $ beast regarded by many as this manufacturers best.
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Old 18th September 2012, 10:33 AM   #1000
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Originally Posted by homemodder View Post
Bob I find the circuit in your book superior to a triple EF, the best advantage to me is stability from oscilation. The circuit Ive been using for a while now which is based on the pioneer from 20 years back goes one further and adds a driver after the four transistor diamond buffer. The diamond buffer also features bootstrapping just as shown in your book. The driver is composed of two transistors in parralell to achieve higher bandwith and lower device capacitances at optimal bias point. The input transistors of the DB are composed of darlington pairs providing very high bandwith and input impedance.
Please could you post a schematic image?
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