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Old 12th February 2012, 02:43 PM   #1
Boscoe is offline Boscoe  United Kingdom
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Join Date: Feb 2010
Location: England
Default My first sort of contribution!...

So I have been on here for 2 years since last Tuesday when I started I knew absolutely nothing about diy audio now I can mostly understand audio electronics and design a lot of different speaker types and understand how they work to quite a depth.

So first I would like to thank the community and the great people here for I would have not learnt nearly as much as I have if this place didn't exist. This is my sort of contribution (hopefully first of many), it's a my go on some modifications of the Pass Labs F5 to suit my needs more. I personally need more power then the F5 can bring to the table and less distortion at the power I want (about ~75W 4ohm). I don't really understand small class A amplifiers in trying to reduce distortion overall by biasing an amplifier heavily you reduce max output power thus inevitably distortion increases as you reach max power out. Combine this with the need for large heat sinks and PSUs for me it isn't a viable solution. On the other hand I love simple circuits and especially those with no capacitors! I will lower the bias current to AB levels too.

So this is what come up with - not much I know but I felt like doing something this morning. Just an extra pair of output devices and limiter removed. Despite what I said above I still need some help with it, I want more gain if that's possible with adding another stage? Perhaps a darlington input with the same FETs? Do the gate resistor values change if I'm using a extra pair of output devices?

I haven't tested my changes yet as I only started work on it this morning and it will take a week or so before I have access to PCB making facilities.

Here's the changed schematic and PCB designs:

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Old 12th February 2012, 04:54 PM   #2
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Join Date: Nov 2004
Location: Germany
When it comes to amplifiers, the factors complexity, power consumption and performance are inherently linked. You cannot have all three equally at the same time.

The performance posted by rather simple circuitry operated in Class A can be quite impressive, but this comes at the cost of considerable current draw in relation to output currents. Going to class B means reduced gain bandwidths (among other kinds of nastiness creeping in), so in order to achieve the same kind of open-loop gain, you have to counteract with more gain stages. You are also more likely to require compensation.

BTW, your schematic has severe problems - you have Q3 and Q4 twice (one pair not even connected to the output no less, and your second R13 and R14s are floating in mid-air, too), and for things to work you need two p-channel devices on top and n-channel ones on the bottom.

For more open-loop gain, you would have to go from the two inverting gain stages that you have now to two inverting gain stages and a buffer (e.g. complementary source follower or diamond buffer). The second gain stage would obviously no longer need to use MOSFETs that beefy then. Compensation may be needed, usually on the second gain stage.

Closed-loop gain in this current feedback design is set by the ratio of the 100R||100R and 10R resistors, as in a non-inverting operational amplifier circuit.
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Old 12th February 2012, 05:12 PM   #3
sbrads is offline sbrads  United Kingdom
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Join Date: Jun 2005
Location: Kent, UK
I've only had a quick look but yes you could increase the gain x2 by removing R7 and R8. There's no compensation so it may oscillate, so try caps across R5 and R6 but they'll need to be quite large values (>1nF) to do anything as 100R is still a very low value for feedback resistors. Perhaps you should increase them to more like 1K and R1 R2 to 100R, then values >100pF may be more like it. Plus you need an input capacitor if you don't want a little bit of DC on the input melting your speaker. The gate resistors are there to stop the output FETs oscillating at VHF (if they're close to the FET) and don't really have much effect at audio frequencies, the main effect of paralleling FETs is the increase of the quite high gate-source capacitance (I've seen 5nF on some) loading the source impedance (about 1k in your circuit). Also, the right hand Q3 and Q4 aren't used for output, a connection missing methinks.

Last edited by sbrads; 12th February 2012 at 05:16 PM.
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Old 12th February 2012, 06:36 PM   #4
Boscoe is offline Boscoe  United Kingdom
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Join Date: Feb 2010
Location: England
Thanks for the responses. I just forgot to put a wire in from the second pair of output fets.
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