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-   -   Non-complementary class AB linearized amp (http://www.diyaudio.com/forums/solid-state/202526-non-complementary-class-ab-linearized-amp.html)

pauljguy 15th December 2011 12:00 AM

Non-complementary class AB linearized amp
 
3 Attachment(s)
Hi,
I designed, built, tested and listened to this amplifier. Its circuitry is a bit different, but I find it sounds very good (very difficult to tell it apart from a tweaked Linn amp using blind, level-matched AB switching), and it does not generate the excessive heat from a class A design.

Its design is based on a non-complementary BJT circuit. It runs
class AB, and uses current amplifying stages instead of voltage
amplifying stages (VAS) to drive the output transistors. The output
stransistors are in a totem-pole configuration, but run common
emitter rather than the usual common collector (emitter follower)
layout. The front end of the amplifier uses a differential compound
pair (Sziklai).

The first transistor after the differential pair is biased such
that instead of cutting off sharply for class AB, it has an
extended non-linear cutoff to minimize the impact of "crossover"
distortion. This base circuit also compensates
for the inherent non-linearity of the "gm doubling" of the output
transistors when run class AB. The result is that over the entire
operating range, the openloop gain of the amp doesn't vary more than
5-10%. Closing the feedback loop with about 60db of loopgain results
low distortion.

measurements using +21/-21 volt power rails:

Output power (.003% distortion) 35 watts @ 4 ohms
output power (.1% distortion) 45watts @ 4 ohms
freq. response: 10Hz-50KHz +0-3db
Low freq. limit set by coupling capacitor, can be eliminated for DC
Slew rate: 5V/us (can be increased but requires 10uh in parallel with 10
ohms in series to load)
Capacitive loads: stable (with 2V/us slew rate) with 1uf low-ESR load.
Distortion (@ 1khz): 2nd harmonic below -90db for 35 watts or less
3rd harmonic below -85db for 35 watts or less
higher harmonics below -90db for 35 watts or less
Output stage protection: output voltage diode clamped to rails
output current limited to 4 amps after 10ms
DC on output: adjustable to zero, stable to a few millivolts.

I enclosed the schematics and an LTSpice ".asc" file to show the gain linearity while the input is DC swept. Plot the derivative of the output voltage "d(V(Vout))". The circuit requires the Cordell models for MJL3281, 2N5089, 2N4403. I have used MPSA56 transistors extensively, and the SPICE model is on the ON Semiconductor site, or just use 2N4403's instead. MPSA56's were popular 'cause I had a whole pile in my transistor bin.

The circuit is a bit of a fluke.... it originally was a class A design - one of the design iterations showed better performance running class AB! You can probably greatly increase the power output with higher voltage rails. I didn't need much power, and I had a pair of transformers scavenged from a few cheapy UPS's that would only do 21 volts DC.

Feel free to use the circuit as you wish, please tell me if there's anything you think that might improve its sound.

Paul G.

AndrewT 15th December 2011 02:32 PM

I'm probably not clever enough to pick up on the subtleties of your overall circuit.
What I see is a dual VAS that has been cascoded. The VAS directly drives the output devices. What's special about that?

Do you have sufficient current gain to drive a load? Particularly a speaker load.

The +IN base sees 110k, the -IN base sees 9k1.
I suspect you have to deliberately unbalance the input LTP to cancel out the input offset current and voltage and thus achieve near zero output offset.

kaos 15th December 2011 03:14 PM

+ 1 on Andrew’s comments. About the only thing I see atypical about the circuit is the output stage bias feedback. One thing you could try doing is connecting the RC’s of C100 and C200 to the collectors of the 2nd stage cascodes instead of the collectors of the VAS’, may be able to run a lower value of C that way, possibly upping the slew rate. Just a thought, I'm sure you've worked a lot of angles of the design.

pauljguy 15th December 2011 04:16 PM

The output devices are current driven to give voltage translation from the positive rails, and to ignore the effect of the very different base voltages of the output transistors. The current drive allows the output transistors to both run at full gain - there is no feedback as you'd get with an emitter follower, since the base currents are unaffected by the emitter voltages. The cascoding of the driver transistors (Q100,Q200) ensures that the currents remain balanced despite the difference in pwr transistor bases.

The "magic" is in the 470 ohm (R100, R200) base circuit for Q100, Q200. The voltage across that resistor is developed by the input differential circuit. That voltage causes Q100 and Q200 to create collector currents, but the base voltage to collector current relation is non-linear (exponential). As the base drive comes from higher impedance, it becomes more of a current drive, and as such becomes more linear. In effect, you can control the degree of non-linearity of a transistor common emitter stage by the Thevenin resistance of the base drive. In this case, for a 400-500ma output transistor bias current, the value of R100, R200 seems to balance the non-linearity caused by the output transistors and gm doubling.

If I replace the 470 ohm R100, R200 by a high impedance active load, there is a kink as both output circuits go into conduction, and the gain doubles as you'd expect in gm doubling. Note that gm doubling is much reduced in an emitter follower - as you'd expect when you apply the feedback formulas. Using the 470 ohm resistor gives an open-loop gain variation of 5-10% over the full range, compared to a greater than 2:1 variation when using a more conventional circuit. For a given bias current, there is an optimum value of R100, R200.

I have some trouble trying to explain WHY this works, and how to predict the optimum values for R100,R200. During best linearity, it turns out that Vbe of the driver transistor matches Vbe of the output transistor over the full signal range, within a few millivolts. I am not sure what that signifies. Also, the optimum linearity occurs when R100,R200 are approximately the dynamic value of rbe for Q100,Q200.

The other wrinkle is that the non-linearity allows a very gradual cutoff as the output transistors shift out of class A operation. It's very difficult to measure the precise cutoff point, and I don't see any bumps or nicks as the circuit transitions through cutoff. Measuring distortion at lower signal levels is quite difficult, since my equipment is limited to about -105db distortion. There was nothing I could see. I am relying on measured results, not simulated ones. I find that LTSpice did not give me results that were close in the case of distortion limits or high frequency stability, but its good enough to see what direction to go in.

There is definitely enough gain to drive a speaker. The open loop gain of the circuit is about 2000-3000, as computed by LTSpice. When the feedback loop is closed the gain is 10, giving me a loop gain of 200-300, or about 50db. Because of the better linearity, I can use less feedback, and still get overall distortion products of about 90 db below full output.

The driver transistors can supply 50-100ma into the MJL3281 bases. The output transistors have an Hfe of 150, yielding 8-15 amps. That is more than enough current for a 35 watt amp. The limiting circuit will allow high current transients, but will pull back when the average transistor current is greater than 4 amps. The speaker sees twice the current variation for each power transistor.

The amp has inverting type feedback, so the input impedance is about 10k in parallel with R2 (100k). If you make the reasonable assumption that the main input is driven by a voltage source, both bases of the differential pair see about 9.1kohms AC impedance. You are correct at DC conditions. On the other side of the diff input, I should put a 4.7uf cap in series with R13 (9.1k), and add a DC path to ground, about 51 Kohms. That should improve the DC stability and the AC balancing. During the beginning part of the design I didn't use a coupling capacitor, and ran everything DC. That caused a few problems with some signal sources, so the capacitor went in, and I neglected to match the DC circuitry. Thanks for the tip!

By the way... the reference designators (Q100, R200, etc) I mention are from the PDF files I attached above. The LTSpice circuit has quite different reference designators.

Paul G.

AndrewT 15th December 2011 04:36 PM

Quote:

Originally Posted by pauljguy (Post 2821934)
.........The driver transistors can supply 50-100ma into the MJL3281 bases. The output transistors have an Hfe of 150, yielding 8-15 amps.

I will need to read your technical method of operation a few times to understand the working.

But look at the datasheet. There is no way hFE=150 when output current = 15Apk
BTW,
45W into 4r0 would require a peak current capability of ~15Apk without much loss of output voltage, to make it capable of driving a 4ohm reactive speaker for all types of music.
There is no point in testing to see if the amplifier can deliver 15Apk into 0r1. That is quite different.

pauljguy 15th December 2011 05:38 PM

Quote:

Originally Posted by kaos (Post 2821821)
+ 1 on Andrew’s comments. About the only thing I see atypical about the circuit is the output stage bias feedback. One thing you could try doing is connecting the RC’s of C100 and C200 to the collectors of the 2nd stage cascodes instead of the collectors of the VAS’, may be able to run a lower value of C that way, possibly upping the slew rate. Just a thought, I'm sure you've worked a lot of angles of the design.

That would defeat the isolation that the cascode stage gives. Notice that both power transistors are NPN, and one emitter is close to the output voltage, and the other emitter is at the negative rail. One set of cascode collectors has about .5v AC, the other one can vary almost from +rail to -rail. Although at first glance it looks like a complementary emitter follower circuit, it really is two stacked common emitter transistors. The current drive from the cascode forces the same gain from each power transistor.

Without the cascode isolation, signals from the upper power transistor will feed back and unbalance the drivers.

I tried moving the compensation circuit around (it creates a dominant pole), stability seemed best where it is now. It seemed that setting the open loop -3db freq. response to about 8kHz would give stability. The closed loop response is between 50-100KHz. There are two other compensation circuits (R54-C53, R12-C5), they were necessary to keep things stable with a 1uf across the load, running flat out.

I chose a slightly slower more stable amp instead of a faster one with the R-L (10 ohm in parallel with 10uH) in series with the output.

Paul G.

MagicBox 15th December 2011 05:57 PM

I've gotta say, a pretty design :) Effective use of cascodes and I like the current based gain mechanism, essentially you're turning the output devices themselves into a VAS. Also the parallelling of cascode devices is a nice way to disperse power.

The only comment I have that might improve your figures is to lower the feedback resistance, if you can/want to afford a lower impedance input. I think it'd help reduce noise figures.

Is it correct that the bias adjust has to be a multiturn for any sensibly accurate Iq adjustments?

CBS240 15th December 2011 06:23 PM

There appears to be a common mode loop, Q8 acting on the sum of the voltage drop across R50/51. This loop goes back to Q1, modulating the value of the CCS. I've used the same basic concept to bias a VAS, but not including the output stage. Interesting way of biasing quasi output stage.

BTW, J-fets are nice too, especially for CCS.;)

pauljguy 15th December 2011 11:55 PM

Quote:

Originally Posted by MagicBox (Post 2822098)
I've gotta say, a pretty design :) Effective use of cascodes and I like the current based gain mechanism, essentially you're turning the output devices themselves into a VAS. Also the parallelling of cascode devices is a nice way to disperse power.

The only comment I have that might improve your figures is to lower the feedback resistance, if you can/want to afford a lower impedance input. I think it'd help reduce noise figures.

Is it correct that the bias adjust has to be a multiturn for any sensibly accurate Iq adjustments?

I haven't noticed any noise issues - 2N5089's are pretty good for noise, and the AC impedance of the base circuits is around 9kohms. Looking up the specs for 2N5089, it claims less than a 2db noise figure for the audio band. We live in a very quiet area, and I haven't heard any noise while listening to the amp. Putting my ears about 2 inches from the speaker, I can hear a bit of 120Hz, but no hiss. At a foot or two distance I can't hear anything. The speakers are PSB Stratus Gold's. With horns or more efficient speakers you might be able to hear it close up.

It doesn't need any fancy 10 turn pot for bias adjustment. I use a single turn trimpot, and I use either an ammeter or the bi-colour LED circuit shown in the optional circuits above. Changing the output stage's current while monitoring the distortion shows a broad minimum of distortion. Setting the current plus or minus 100 ma from the 400ma optimum changes the distortion by one or two db.

What really messed up the distortion was when the circuit oscillated at several MHz. The RF would not show up at the output (except as distortion as it changed amplitudes). Even with a 100 MHz 'scope, the RF amplitudes were barely visible, and they'd change depending on the audio signal. Once the circuit was properly compensated, a lot of distortion and sporadic RF disappeared.

Paul G.

pauljguy 16th December 2011 12:09 AM

Quote:

Originally Posted by CBS240 (Post 2822147)
There appears to be a common mode loop, Q8 acting on the sum of the voltage drop across R50/51. This loop goes back to Q1, modulating the value of the CCS. I've used the same basic concept to bias a VAS, but not including the output stage. Interesting way of biasing quasi output stage.

BTW, J-fets are nice too, especially for CCS.;)

It takes about 2 amps through R50-R51 before Q8 begins to conduct. This is the overcurrent control. C12 smooths out the waveform so that the overcurrent reacts to average output current. (With a sine wave output, the voltage across R50-R51 appears as a rectified sine wave)

The operating point is controlled by the current source in the long-tailed pair. It's quite stable, and D5,D6 are mounted on the transistor heatsinks to keep things from getting too hot. Just to be sure, I ran both channels full out into a short circuit, and let it cook for about 20 minutes. Once the shorts were removed, the bias current was maybe 100ma lower than it should have been, until things cooled down.

Paul G.


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