My new design or updated old one

[astankov]

Well I decide to make some changes to my old project: What you think about this schematic?

As a start VAS is now in darlington configuration and instead of bootstrap I use a current generator. Also added a gate protection zeners - are they connected right way on the schematic and what voltage they must be?

The new schematic is on the first picture. It is tested only in simulation and results are promising so I want to make a "real world" test. Before building it I want to know what you think for the project , is there something obviously wrong on it that need attention. On the second picture is 1Khz sine wave test and distortion and on the third clipping behavior. In my next posts I will add more tests in pictures.

Cheers!

Edit 02.02.2012 because of an unsuccessful real world build I decided to radically change the concept of the schematic:

1. Move trimmer for dc offset from emitters of the input LTP to emitters of the
transistors in the current mirror.

2. Changed VAS from EF buffered to cascoded.

3. OPS is now in quasicomplementary configuration.

4. Increased the supply voltage to +-50V and corrected the NFB for it.

Schematic can be found in post 131. The given transistors are just for suggestion. You can use any with similar properties.
Also we have PCB thanks to the best PCB maker in the world - Alex MM (Thanks very much Alex )
PCB also can be found in post 131.


Have fun!

[astankov]

On first picture 1Khz square wave response , on second 10Khz sine wave and distortion and on the third 10Khz square wave response.

[Mooly]

Nothing obviously amiss other than polarity of caps as drawn.

Simulation is only a small part of the story.

Try it with a real reactive load.

What happens if the output is loaded with a small capacitance of say 10nf and 100nf and 1uF ?

T3 and T4 base base bias networks are slightly unequal at DC (R8 51K).

[Tekko]

Pretty similar to quasi's circuit apart from the complementary output and quite similar to mine except upside down.

[astankov]

I know that simulation is only a small part of the story but gives me a promising results thats why I want to test in real conditions and if as you say everything looks normal I will go ahead.

I also made a sim with capacitor in the output. On the first picture is square wave response on 1Khz and 10nF in the output , on second 10khz and 10nF , on the third 1khz and 100nF

[astankov]

More pics. First is 10khz and 100nF , on second 1khz and 1uF , on third 10khz and 1uF. At 20Khz response is similar to 10khz response.

Looks good but only real test will tell the true.

About DC imbalance of IS I agree R8 must be 56K

You dint say anything about gate zeners? What voltage to use?

[Nico Ras]

Not to shoddy at all, would work in practice as Mooly said. Your question about the zener diodes: use 15V.

[Leon08]

Darlington VAS is more difficult to stabilize.It works in simulation, but not everytime in reallife.I suggest to use cascode VAS.

[CBS240]

Its not Darlington VAS, but EF buffered VAS. Not too bad, T13 collector is to gnd not VAS output node, however I do like cascode VAS as well.

[Mooly]

It will be interesting to compare simulation with a real build. Your simulated square wave response is essentially perfect... how well will that translate to a real circuit ?