Well I decide to make some changes to my old project: http://www.diyaudio.com/forums/solid-state/171882-what-you-think-about-schematic.html
As a start VAS is now in darlington configuration and instead of bootstrap I use a current generator. Also added a gate protection zeners - are they connected right way on the schematic and what voltage they must be?
The new schematic is on the first picture. It is tested only in simulation and results are promising so I want to make a "real world" test. Before building it I want to know what you think for the project , is there something obviously wrong on it that need attention. On the second picture is 1Khz sine wave test and distortion and on the third clipping behavior. In my next posts I will add more tests in pictures.
Cheers!
Edit 02.02.2012 because of an unsuccessful real world build I decided to radically change the concept of the schematic:
1. Move trimmer for dc offset from emitters of the input LTP to emitters of the
transistors in the current mirror.
2. Changed VAS from EF buffered to cascoded.
3. OPS is now in quasicomplementary configuration.
4. Increased the supply voltage to +-50V and corrected the NFB for it.
Schematic can be found in post 131. The given transistors are just for suggestion. You can use any with similar properties.
Also we have PCB thanks to the best PCB maker in the world - Alex MM (Thanks very much Alex 🙂 )
PCB also can be found in post 131.
Have fun! 😀
As a start VAS is now in darlington configuration and instead of bootstrap I use a current generator. Also added a gate protection zeners - are they connected right way on the schematic and what voltage they must be?
The new schematic is on the first picture. It is tested only in simulation and results are promising so I want to make a "real world" test. Before building it I want to know what you think for the project , is there something obviously wrong on it that need attention. On the second picture is 1Khz sine wave test and distortion and on the third clipping behavior. In my next posts I will add more tests in pictures.
Cheers!
Edit 02.02.2012 because of an unsuccessful real world build I decided to radically change the concept of the schematic:
1. Move trimmer for dc offset from emitters of the input LTP to emitters of the
transistors in the current mirror.
2. Changed VAS from EF buffered to cascoded.
3. OPS is now in quasicomplementary configuration.
4. Increased the supply voltage to +-50V and corrected the NFB for it.
Schematic can be found in post 131. The given transistors are just for suggestion. You can use any with similar properties.
Also we have PCB thanks to the best PCB maker in the world - Alex MM (Thanks very much Alex 🙂 )
PCB also can be found in post 131.
Have fun! 😀
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Nothing obviously amiss other than polarity of caps as drawn.
Simulation is only a small part of the story.
Try it with a real reactive load.
What happens if the output is loaded with a small capacitance of say 10nf and 100nf and 1uF ?
T3 and T4 base base bias networks are slightly unequal at DC (R8 51K).
Simulation is only a small part of the story.
Try it with a real reactive load.
What happens if the output is loaded with a small capacitance of say 10nf and 100nf and 1uF ?
T3 and T4 base base bias networks are slightly unequal at DC (R8 51K).
Pretty similar to quasi's circuit apart from the complementary output and quite similar to mine except upside down.
I know that simulation is only a small part of the story but gives me a promising results thats why I want to test in real conditions and if as you say everything looks normal I will go ahead.
I also made a sim with capacitor in the output. On the first picture is square wave response on 1Khz and 10nF in the output , on second 10khz and 10nF , on the third 1khz and 100nF
I also made a sim with capacitor in the output. On the first picture is square wave response on 1Khz and 10nF in the output , on second 10khz and 10nF , on the third 1khz and 100nF
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More pics. First is 10khz and 100nF , on second 1khz and 1uF , on third 10khz and 1uF. At 20Khz response is similar to 10khz response.
Looks good but only real test will tell the true.
About DC imbalance of IS I agree R8 must be 56K
You dint say anything about gate zeners? What voltage to use?
Looks good but only real test will tell the true.
About DC imbalance of IS I agree R8 must be 56K
You dint say anything about gate zeners? What voltage to use?
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Not to shoddy at all, would work in practice as Mooly said. Your question about the zener diodes: use 15V.
Darlington VAS is more difficult to stabilize.It works in simulation, but not everytime in reallife.I suggest to use cascode VAS.
Its not Darlington VAS, but EF buffered VAS. Not too bad, T13 collector is to gnd not VAS output node, however I do like cascode VAS as well.😉
It will be interesting to compare simulation with a real build. Your simulated square wave response is essentially perfect... how well will that translate to a real circuit ?
Well I think is too good to be true will be different in reality.
I like SE VAS and will use it , it probably need do make compensation cap value 2 or 3 times bigger to prevent oscillation but this in real tests.
The problem is that my house is being repaired now and all my stuff is not with me so real test will probably wait month or two and the even bigger problem is that I dont have a oscilloscope for the tests but I will see what I can do to take one.
You suggest me to use 15V zeners will do thanks for the advice.
Cheers!
Is the pot for adjusting offset really necessary? Surely you've got any DC problems covered by having C4 in the feedback loop?
Trim pot is not absolutely necessary but you need to match T3 and T4 and that is not always possible. Having the trim pot makes the schematic less pretentious to building elements.
Other reason is that I like DC offset to be below 5mV.
Other reason is that I like DC offset to be below 5mV.
At least PCB!
After many hours of work I finally created a PCB for this schematic.
It is my first PCB so I expect you to tell me where can be improved or pointing me a problematic area. I think I don't have wrong tracks but my eyes are tired now and it is possible to have some.
If everything is OK will go to a real test because I'm waiting quite a long for it and my hands are so itchy now .
After many hours of work I finally created a PCB for this schematic.
It is my first PCB so I expect you to tell me where can be improved or pointing me a problematic area. I think I don't have wrong tracks but my eyes are tired now and it is possible to have some.
If everything is OK will go to a real test because I'm waiting quite a long for it and my hands are so itchy now .
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Haven't checked every detail but the obvious improvement is to take the negative feedback point/s from a short spur that then goes off to the speaker output. The distortion is magnitudes greater than it needs be as it is. Pleanty of space at the left to do that.
Thanks for the advice!
Be more critical please it can't be the perfect PCB more or less it is my first. Probably have something more to improve.
It's OK... but I haven't checked it part for part...
What would I look at differently. Maybe some local decoupling nearer the FET's. You could use rail to rail something like a 0.1uf cap just to keep supply impedance down or create ground areas around the FET's and use a small cap/s (say 10uf and 0.1uf) from drains to ground.
When you come to actually make the board those pads will look very small and be fragile. Make them all as large as you can, particularly the FET's. Maybe rectangular. Make any high current carrying tracks as thick as possible. Look at the pads here,
http://www.diyaudio.com/forums/head...-ended-class-headphone-amp-2.html#post2095817
What would I look at differently. Maybe some local decoupling nearer the FET's. You could use rail to rail something like a 0.1uf cap just to keep supply impedance down or create ground areas around the FET's and use a small cap/s (say 10uf and 0.1uf) from drains to ground.
When you come to actually make the board those pads will look very small and be fragile. Make them all as large as you can, particularly the FET's. Maybe rectangular. Make any high current carrying tracks as thick as possible. Look at the pads here,
http://www.diyaudio.com/forums/head...-ended-class-headphone-amp-2.html#post2095817
Changes made according to the advices from the previous post.
I made all tracks thicker where was possible specially GND and +V/-V . All external connections and FET connections have a bigger square pads now. For the decoupling I connected a 0.1uF cap between the power tracks because creating a GND area around FET's is impossible and will require rebuilding of the board.
Thanks for the advices! I'm open for more of them.
I made all tracks thicker where was possible specially GND and +V/-V . All external connections and FET connections have a bigger square pads now. For the decoupling I connected a 0.1uF cap between the power tracks because creating a GND area around FET's is impossible and will require rebuilding of the board.
Thanks for the advices! I'm open for more of them.
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