Complementary JFET-JFET cascode input, BJT VAS-Drivers, Lateral Output - diyAudio
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Old 15th October 2011, 02:34 PM   #1
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Default Complementary JFET-JFET cascode input, BJT VAS-Drivers, Lateral Output

Somewhat high performance amplifier.

Complementary input with 2SK170/2SJ74 cascoded by 2SK246/2SJ103.

About 4 mA through each 2Sk170/2SJ74, 8 mA through R2.

Darlington VAS'es with 2SC3503/2SA1381. 9 mA though the VAS section.

Driver section with 10 mA through 2SC3503/2SA1381 pre-drivers and about 50 mA through MJE15032/MJE15033 drivers.

Output consists of 4 pairs of 2SK1058/2Sj162 Lateral FET's biased at 150 mA each.

Curerntly only done in simulation but the results are good enough for me to start building it soon, once I get the layout done.
Attached Images
File Type: png Schematic.png (84.8 KB, 888 views)

Last edited by Neutrality; 15th October 2011 at 02:53 PM.
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Old 15th October 2011, 02:42 PM   #2
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The tests below were done WITH the input filter and 470 uF cap in the NFB network.

THD-1 and THD-20 simulation results. 8 Ohm load.

THD-1
1 W : 0.0000375%
30 W : 0.000234%
60 W : 0.000391%
90 W : 0.000495%

THD-20
1 W : 0.000556%
30 W : 0.005390%
60 W : 0.006296%
90 W : 0.020645%


Attached images shows output frequency response and squarewave performance plots at 1 KHz and 20 KHz.

Gain is about 26.6 dB

Frequency response plot shows 26.2 dB at 1 Hz and a high frequency -3 dB point of 195 KHz.
Attached Images
File Type: png Output-frequency response.png (53.4 KB, 809 views)
File Type: png Squarewave1KHz.png (17.2 KB, 701 views)
File Type: png Squarewave20KHz.png (17.7 KB, 674 views)

Last edited by Neutrality; 15th October 2011 at 02:50 PM.
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Old 15th October 2011, 02:48 PM   #3
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Below tests were done WITHOUT the input filter and the 470 uF cap in the NFB network.

Attached are Loop gain and Slewrate measurement plots.

Loop gain plot shows about 69 degrees phase margin and about 10 dB gain margin.

Slewrate measurement plot shows a slewrate of about 60V/500nS, which scaled to 1us gives a slewrate of about 120 V/uS.
Attached Images
File Type: png Loopgain-Gain-phase-margin.png (54.5 KB, 660 views)
File Type: png Slewrate.png (31.7 KB, 102 views)
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Old 15th October 2011, 03:12 PM   #4
Bonsai is offline Bonsai  Taiwan
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Nice, but do you need the double emiter follower if you are using a FET output stage? You should be able to drop this to a simple emitter follower buffer between the VAS and the FET's.

Your loop gain plot looks a bit optimistic and in practice you may run into instability issues - I would shoot for a unity gain cross over frequency of around 1-2MHz. You can accomplish this by providing more degeneration on the JFETS, or increasing Cdom - but this latter appproach will cause your slrew rate to decrease unless you increase the LTP current.

The 10pF comp fap across your feedback resistor also looks a bit on the high side. This value should be set during development of the physical prototype, and it needs to be tweaked to give the optimum gain margin. For a feedback resistor values of 5k, this typically means about a 5-10pF capacitor.

You may want to consider using TMC instead of the miller comp currently shown in your designs - this will get your distortion down another 2x or more.

Good luck with your project.
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Last edited by Bonsai; 15th October 2011 at 03:19 PM.
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Old 15th October 2011, 03:20 PM   #5
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Single EF driver stage is more than enough for lateral FETs, looks like BJT amp is adapted for laterals.
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Old 15th October 2011, 03:20 PM   #6
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Quote:
Originally Posted by Bonsai View Post
Nice, but do you need the double emiter follower if you are using a FET output stage? You should be abel to drop this to a simple emitter follower buffer between the VAS and the FET's.

You may want to consider using TMC instead of the miller comp currently shown in your designs - this will get your distortion down another 2x or more.

Good luck with your project.
I tried with just a single emitter follower, THD-20 stayed at atleast 0.01% THD from 30 W and up. I think it was about 0.022% THD-20 at 60 W output. With the double emitter follower the THD-20 was alot lower to the tune of about 3x.

A single emitter follower loaded the VAS too much. Going from a single emitter follower to double emitter follower reduced the load on the VAS from 750uA to about 70-80uA. Which resulted in a nice reduction of THD-20.

Distortion wise I am more than happy at the current level, TMC really isnt needed.
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Old 15th October 2011, 03:25 PM   #7
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Quote:
Originally Posted by Workhorse View Post
Single EF driver stage is more than enough for lateral FETs, looks like BJT amp is adapted for laterals.
Like I said in my reply to Bonsai, I started out with just a single emitter follower in the driver section. I didnt think it would be a problem. But my THD-20 simulations proved otherwise. Once I added the pre-drivers the THD-20 finally was where I expected it to be.

So it is NOT a BJT amplifier adapted to FET's. I started out with wanting to design a FET output amp.

Not my fault that it ended up looking like a BJT amp with FET outputs.
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Old 15th October 2011, 03:28 PM   #8
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Quote:
Originally Posted by Bonsai View Post

Your loop gain plot looks a bit optimistic and in practice you may run into instability issues - I would shoot for a unity gain cross over frequency of around 1-2MHz. You can accomplish this by providing more degeneration on the JFETS, or increasing Cdom - but this latter appproach will cause your slrew rate to decrease unless you increase the LTP current.

The 10pF comp fap across your feedback resistor also looks a bit on the high side. This value should be set during development of the physical prototype, and it needs to be tweaked to give the optimum gain margin. For a feedback resistor values of 5k, this typically means about a 5-10pF capacitor.
Good points.

I'll take them into consideration.

Last edited by Neutrality; 15th October 2011 at 03:31 PM.
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Old 15th October 2011, 04:13 PM   #9
Bensen is offline Bensen  Belgium
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Just out of curiosity; have you tried or considered a FET driver stage instead of the 3EF?

You are running the drivers very hot I see, personaly I would have there about 20 tot 30mA. Have you seen an improvement somewhere with increasing the bias throught the drivers?

Greetz
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Old 15th October 2011, 04:51 PM   #10
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Originally Posted by Bensen View Post
Just out of curiosity; have you tried or considered a FET driver stage instead of the 3EF?

You are running the drivers very hot I see, personaly I would have there about 20 tot 30mA. Have you seen an improvement somewhere with increasing the bias throught the drivers?

Greetz
I have considered a FET driver stage and am still considering it.

Driver current is something that could be adjusted. 20 mA would be just as reasonable.

I will be trying a FET driver stage tonight or sometime tomorrow.

If it comes close in performance I might go that way.

My goal is less than 0.01% THD-20 at 60 W into an 8 Ohm load as a minimum.

Last edited by Neutrality; 15th October 2011 at 04:54 PM.
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