Complementary JFET-JFET cascode input, BJT VAS-Drivers, Lateral Output - Page 2 - diyAudio
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Old 15th October 2011, 05:25 PM   #11
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Quote:
Originally Posted by Neutrality View Post
I have considered a FET driver stage and am still considering it.

Driver current is something that could be adjusted. 20 mA would be just as reasonable.

I will be trying a FET driver stage tonight or sometime tomorrow.

If it comes close in performance I might go that way.

My goal is less than 0.01% THD-20 at 60 W into an 8 Ohm load as a minimum.
Well, tried that, with irf510/9510 and irf610/9610.

Didnt work, 0.01% THD-20 for the 510/9510 pair and 0.02% for the 610/9610 pair.

The load on the VAS was still only 70-80 uA so that wasnt the problem.

I ran them with about 50 mA through them. Maybe they like a somewhat higher bias.

EDIT : 200 mA through 610/9610, same 0.02% THD-20. Looks like FET drivers in this amp is a dead end.

Last edited by Neutrality; 15th October 2011 at 05:29 PM.
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Old 15th October 2011, 06:49 PM   #12
Bonsai is offline Bonsai  Taiwan
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Recheck your output stage bias current if you ever adjust R3 or R27 in your sims. Because you are runnung at a high driver current, the base currents flowing throught your base stoppers on the EF transistors cause enough of a voltage drop to cause shifts in the bias point on the output devices. I would agree with the poster above, on a FET output stage, the drivers don't need to run at more than 20-30mA and still remain in class A
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Old 15th October 2011, 07:12 PM   #13
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I always check the bias points, whenever I change R3 or r27 or adjust the bias.

Bias for the output stage is always set at 150 mA per FET.
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Old 16th October 2011, 12:25 AM   #14
mlloyd1 is offline mlloyd1  United States
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just a tip - might be worth it to go to the hafler site, download the manual for the XL-280 and review the schematic.

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Old 16th October 2011, 11:02 AM   #15
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I went back and did some more simulations with just one set of drivers. Out went the MJE15032/MJE15033 and now I'm only using 2SC3503/2SA1381 as drivers.

With 9 mA through them and still 150 mA per FET THD-20 is now 0.0068XX% at 60 W into 8 Ohm. Not quite as good as with the pre-driver/driver combo that got 0.0062XX% at 60 W into 8 Ohm, but taking into account that this is just simulation it could be considered just as good.

Slewrate is the same, both 1KHz and 20KHz squareware response look just as good.

Only downside is a reduction in phase margin but the gain margin shows an increase. Going from 61 to 50 degrees phase margin and from 10 dB to 18 dB gain margin.

But still, with this being just a simulation, performance is more or less the same, but with one less driver stage.

Took me all of 5 minutes to throw one driver stage out and retain more or less the same performance.
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Old 16th October 2011, 01:19 PM   #16
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Quote:
Originally Posted by Neutrality View Post

Only downside is a reduction in phase margin but the gain margin shows an increase. Going from 61 to 50 degrees phase margin and from 10 dB to 18 dB gain margin.
Apparently I cant read a Loop gain plot correctly.

What I ment to say was that phase margin stays at around 70 degrees and gain margin is improved to about 12 dB.
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Old 17th October 2011, 03:02 PM   #17
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Preliminary layout, a work in progress.

From input to driver stage is more or less done. But wont rule any smaller tweaks to the layout before I'm done

It is not perfect but just as in more or less all layouts, some compromises have to be made.
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Old 18th October 2011, 04:10 PM   #18
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Layout almost done.

Considering some changes to the cascode, from JFET to BJT.

Alot easier to go with a BJT cascode.

However, simulations shows that the higher Vds voltage across the input 2Sk170/2SJ74 JFET, the lower THD-20 I get.

Somewhere around 20 Vds across the input JFETs give me the optimum THD-20 values. That is very close to the max Vds of the 2SJ74 JFET.

Difference from 20 Vds and something like 15 Vds is only an increase in THD-20 of 0.0015%. Not alot.
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Old 18th October 2011, 04:21 PM   #19
AndrewT is online now AndrewT  Scotland
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assuming a fixed maximum voltage swing at the input fets, then with a high Vds that fixed input/output swing is a large portion of the total applied voltage.
Double or triple the applied voltage and the input/output swing becomes a much smaller part of the applied voltage.
That is what reduces distortion. The same logic applies to a VAS stage.
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Old 18th October 2011, 04:25 PM   #20
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Nelson says that the jfets operate safely up to 30v if dissiaption is maintained
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