mixed (lateral + vertical) MOSFET paralelling

[franzm]

Hello,
Has enyone tried mixed (lateral + vertical) MOSFET paralelling?

The laterals have low gm and threshold voltage and are biased into class A (or high current AB) and will work mainly in class A. The verticals have higher gm and threshold voltage and are biased into class C or B (or low current AB) to prevent thermal runaway. There ist only one bias voltage source for both transistor pairs (assuming a complementary source follower output stage topology).
As the output current raises, the transistors will conduct gradually: first the laterals and then the verticals. Due to the higher gm of
the verticals, they will supply (or sink) the biggest part of the output current at high drive levels so the laterals won't be overloaded.
The source resistors of the transistors (the laterals mainly) are choosen to divide the currents between the transistors in a convenient ratio.
In order to achieve a high gm, one could increase the number of verticals.
This topology could be the best of two worlds: the better linearity and thermal stability of the lateral for the "first Watt" and the power handling capability of the verticals for higher output levels.

[NMOS]

Originally Posted by franzm

Hello,
Has enyone tried mixed (lateral + vertical) MOSFET paralelling?

The laterals have low gm and threshold voltage and are biased into class A (or high current AB) and will work mainly in class A. The verticals have higher gm and threshold voltage and are biased into class C or B (or low current AB) to prevent thermal runaway. There ist only one bias voltage source for both transistor pairs (assuming a complementary source follower output stage topology).
As the output current raises, the transistors will conduct gradually: first the laterals and then the verticals. Due to the higher gm of
the verticals, they will supply (or sink) the biggest part of the output current at high drive levels so the laterals won't be overloaded.
The source resistors of the transistors (the laterals mainly) are choosen to divide the currents between the transistors in a convenient ratio.
In order to achieve a high gm, one could increase the number of verticals.
This topology could be the best of two worlds: the better linearity and thermal stability of the lateral for the "first Watt" and the power handling capability of the verticals for higher output levels.

you can handle with 2 vertical fets about 200 Watt RMS....