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Old 31st December 2013, 12:52 AM   #91
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Quote:
Originally Posted by jkuetemann View Post
I'll take another look at further optimization of the grounds. I do have a preference for one ground connection to the PCB from the PSU if possible.

One thought about the CCSs is to link them to each other rather than ground. Seems to work well in simulation, any thought about it in a real implementation?
the G1/2 scheme has just one end connection to ground. "Poke around" for
"star within a star" grounding. How it works .... center point of your main star
has equal R/L from each main cap or output (cancels out) .. to pull a trace off
there (as you have done) assures that any smaller star will have these same attributes.

I see this almost universally on low to high end amps. They usually go further and physically separate the PS/OPS from the IPS .
They even take the IPS rails direct from the main PS caps (not the OPS traces) , as well.
An example below..... (they run black wires to the zoble and G2 under board.)
Amp is dead silent.

Sims on both of my CFA's show minimal difference between rail and ground referenced CCS's (< 1DB PSRR).


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File Type: jpg ground example.jpg (57.3 KB, 127 views)
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Old 31st December 2013, 02:16 AM   #92
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OK, is this a better approach than the last update? Or should I create a trace to go away from the ground fast-on a short way and create a new star there?

As I see it there is a star on the bottom (the 'dirty' one) and a star on the top (the 'clean' one) connected by the fast-on itself.

As I understand grounding thus far anything that potentially carries high and / or irregular currents needs to return to the 'dirty' ground. This would be any onboard reservoir capacitors, decoupling capacitors, Zobel networks and the speaker return. The 'clean' ground simply becomes a reference for things like the input stage and feedback network.
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Old 31st December 2013, 02:41 AM   #93
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YES !

This is even more crucial for CFA , with that 100mA FB return. The same as
you took the current FB from your OPS center point , return it to a "center point" (ground).

On a smaller PCB , the lines gets blurred as far as "G1-G2" (everything is close).
Sansui (and my PCB) are big ! Too many "black wires" for each individual
ground return.

Layout is an art - study the "art" (OEM's)

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Old 31st December 2013, 03:20 AM   #94
rsavas is offline rsavas  Canada
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Good work guys.
Layout is an art :-) more like a science. I think that it became a science with the introduction of eCAD, gone was mylar/tape. We used to have layout girls, who bascially knew very little if anything of electronics. They were the artists :-) Working on Cadnetix Unix box. That is all the computer did, was eCad, but it did have 10M Ethernet. Had to sit with them at times throughout the layout process until backend processing.
ostripper, I agree 100%, learn from how other have done their layouts, tried and tested. hifiengine.com has many of the old SM's as examples of mostly 1 layer pcb's. We are very fortunate to have multilayer pcb's these days.
Learn to use ground planes as well, since they can be very helpful in many ways.
Comes down to thinking like an electron, which way did he go :-)
Good luck with your project, if you fab at Futurelect, let us know how it works out. I have considered them as well.
If you want me to check the gerber/drill data, I can do a quick sanity check. RS-274x format is the standard to use these days. Just post it.
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Old 31st December 2013, 03:56 AM   #95
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@rsavas - Having not yet used a board house (and therefore not prepared the files before) I have zipped up my Gerbers and Excellon files for review.

Anyone who cares to have a look to see if there are any errors it would be appreciated.
Attached Files
File Type: zip VSSAv2revB.zip (17.3 KB, 20 views)
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Old 31st December 2013, 09:23 AM   #96
alex mm is offline alex mm  Europe
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...... silkscreen layer it's not OK , empty image when import file......
Happy New Year to all members
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Old 31st December 2013, 11:53 AM   #97
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Quote:
Originally Posted by alex mm View Post
...... silkscreen layer it's not OK , empty image when import file......
Happy New Year to all members
Alex
Alex,

Thanks for taking a look. I just checked my source and downloaded my own file from the forum and the silkscreen layer appears to be fine (opened with the Pentalogix viewer). Not sure why you saw a blank....

Edit - There is a 'mechanical' layer that IS blank. I meant to remove that.
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Old 31st December 2013, 01:49 PM   #98
rsavas is offline rsavas  Canada
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Hi Jason,

I read your files into GerbTool v15. It complained about one aperture when loading 'BottomSoldermask.gbr". Did not seem to make any difference from what I can tell.
Warning: D19 has zero size.
Not sure why your CAD tool would create a aperture of "0" size. It might be how the pcb outline is displayed.
You have the pcb outline on all layers which is usually not the way to do it. I usually put it on the silk layers and the mechanical or documentation/fab layer only. Maybe your CAD tool works only this way, so you have no choice. Most fab house say you have to define the outline on one layer, usually being the doc/fab layer and not the actual copper layers, since they probably need to edit it out for fab.
Your mech/documentation layer has no dimensions of the finished pcb or any fabrication notes, which leaves it wide open for the fab house to interpret what you want them to do as far as choice of materials, soldermask, pcb thickness, etc, the list can be long. I realize that this info can and usually does get defined in the work order, but ... If you do not get what you want, then you have no fall back as you have not documented clearly, what you want in the fab files which is very important.
Your holes for "2SJ,2Sk,KSC,KSA and the two mounting holes are defined as plated but have no annual ring. This can flag as a DRC exception, as they usually ask for a minimum annular ring as part of the fab process. To be sure, could ask the fab house if they will accept a PTH with no annular ring.
There are many pcb houses that will analyze your data, free of charge, even without submitting a work order.
The rest of the PTH look to have sufficient annular rings.
You have no ref des on you top silk, only values, why? I know it is a small pcb and you know your design well, it is just unusual that it is missing this rather important info.
I'd say that your data is pretty good to go with and what I said above may or may not flag any feedback. Sometimes they see these issues and correct them for the process and you never get any feedback. That depends on who you work with.

Regards and best wishes in the New year
Rick


Information: Begin Log: Tuesday, December 31, 2013 - 09:05
Information: Begin Import File(s) - (09:06:31)
Information: Importing extended Gerber file: TopCopper.gbr
Information: Import Completed Successfully.
Information: End Import File(s) - (09:06:32)
Information: Begin Import File(s) - (09:07:16)
Information: Importing extended Gerber file: BottomCopper.gbr
Information: Remapping: D14 to D11.
Information: Remapping: D15 to D14.
Information: Remapping: D16 to D15.
Information: Remapping: D17 to D19.
Information: Remapping: D18 to D17.
Information: Remapping: D19 to D18.
Warning: D19 has zero size.
Information: Import Completed Successfully.
Information: End Import File(s) - (09:08:06)
Information: Begin Import File(s) - (09:08:38)
Information: Importing extended Gerber file: TopSoldermask.gbr
Information: Remapping: D11 to D23.
Information: Remapping: D12 to D24.
Information: Remapping: D13 to D23.
Information: Remapping: D14 to D25.
Information: Remapping: D15 to D26.
Information: Import Completed Successfully.
Information: End Import File(s) - (09:08:38)
Information: Begin Import File(s) - (09:09:08)
Information: Importing extended Gerber file: BottomSoldermask.gbr
Information: Remapping: D11 to D23.
Information: Remapping: D12 to D24.
Information: Remapping: D13 to D23.
Information: Remapping: D14 to D25.
Information: Remapping: D15 to D26.
Information: Import Completed Successfully.
Information: End Import File(s) - (09:09:09)
Information: Begin Import File(s) - (09:09:31)
Information: Importing extended Gerber file: TopSilkscreen.gbr
Information: Remapping: D11 to D27.
Information: Remapping: D12 to D28.
Information: Remapping: D13 to D29.
Information: Remapping: D14 to D30.
Information: Remapping: D15 to D31.
Information: Remapping: D16 to D32.
Warning: One or more zero length draws converted to flashes.
Information: Import Completed Successfully.
Information: End Import File(s) - (09:09:31)
Information: Begin Import File(s) - (09:09:58)
Information: Importing extended Gerber file: Mechanical.gbr
Information: Import Completed Successfully.
Information: End Import File(s) - (09:09:59)
Information: Importing C:\Projects\VSSAv2revB\DrillFile.DRL
Information: Import Complete.
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Old 31st December 2013, 05:12 PM   #99
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Quote:
Originally Posted by rsavas View Post
Hi Jason,

I read your files into GerbTool v15. It complained about one aperture when loading 'BottomSoldermask.gbr". Did not seem to make any difference from what I can tell.
Warning: D19 has zero size.
Not sure why your CAD tool would create a aperture of "0" size. It might be how the pcb outline is displayed.
You have the pcb outline on all layers which is usually not the way to do it. I usually put it on the silk layers and the mechanical or documentation/fab layer only. Maybe your CAD tool works only this way, so you have no choice. Most fab house say you have to define the outline on one layer, usually being the doc/fab layer and not the actual copper layers, since they probably need to edit it out for fab.
Your mech/documentation layer has no dimensions of the finished pcb or any fabrication notes, which leaves it wide open for the fab house to interpret what you want them to do as far as choice of materials, soldermask, pcb thickness, etc, the list can be long. I realize that this info can and usually does get defined in the work order, but ... If you do not get what you want, then you have no fall back as you have not documented clearly, what you want in the fab files which is very important.
Your holes for "2SJ,2Sk,KSC,KSA and the two mounting holes are defined as plated but have no annual ring. This can flag as a DRC exception, as they usually ask for a minimum annular ring as part of the fab process. To be sure, could ask the fab house if they will accept a PTH with no annular ring.
There are many pcb houses that will analyze your data, free of charge, even without submitting a work order.
The rest of the PTH look to have sufficient annular rings.
You have no ref des on you top silk, only values, why? I know it is a small pcb and you know your design well, it is just unusual that it is missing this rather important info.
I'd say that your data is pretty good to go with and what I said above may or may not flag any feedback. Sometimes they see these issues and correct them for the process and you never get any feedback. That depends on who you work with.

Regards and best wishes in the New year
Rick
Thanks for the review, Rick. I'm new to preparing files for a board house so I don't know what the conventions are supposed to be. I'm using Abacom's Sprint Layout 5 and am not sure what the best tools are for reviewing the Gerbers but am finding the Pentalogix ViewMate free version doesn't tell you much.

I believe I had the board outline checked when exporting each layer. I'll try to be sure to only include it on the silk / outline layer.

The fab layer - do I just put text on that to say what I'm looking for?

My mounting holes have the plating through option off when I check them. The ones on the 2SJ / 2SK are for two purposes. The larger is just for creating an area in my filled zone devoid of copper and the actual hole is for mounting. I manually edited out the large one from the Excellon drill file but enabled the copper 'punch out' in the Gerber to create the clearance I wanted. This is incorrect? I'm not sure I can just erase copper from within a filled area.

The reference designations were left off in favour of the actual values (and this wasn't actually complete - no values on my capacitors ) because the DRC checking complained the silkscreen was too thin if I make the text small enough to put on both. Given a one or the other scenario, I opted for the value. Another no-no I appear to have made.

I will review the design and re-export the files to see if they come out better. Again thanks for your efforts in helping me. Posting or PMing some dos and don'ts would be very helpful if you care to share some general guidelines.
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Old 31st December 2013, 05:58 PM   #100
rsavas is offline rsavas  Canada
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Jason,

I am un-familiar with your CAD pkg, they all have their particularities etc, so I can not comment on the operation of the CAD pkg you have. I am like the pcb house, I just look at the data that it puts out.

Since my CAD pkg, Orcad makes the stackup/fab info automatically I use it. With other CAD pkg's you can make a library component, drawn on a doc layer to be placed of the pcb, so it comes through with the gerber data for that layer or when you have the layer enabled for display.

You will know what is a real no-no, not by me, but the pcb fab and your results if they meet what you intended it to be.

With your CAD package, it puts all drills together and does not separate plated from non. Even though this is what you want.
The pcb house has no way to know for sure as you present the data, since you have put them all together and you have no notes of what is to be plated and not. Basic assumption is all to be plated!!
They will see a hole the same size as a pad and ? what do you want? Could hold up the process, since they need to know what to do. NPLT holes are done after the plating process is done.
It is best to just plate all the holes and leave a minimum annular ring, unless you specifically want a NPTH. In this case make the pad(s) smaller than the drill or FHS(Finished Hole Size). Say 1/2 the FHS.

Nothing wrong with any Gerber viewer. I am sure the free versions could very well have many capabilities dis-abled. For you it a basic sanity check.

I will attach a fab drawing that I sent along with my last pcb fab done at Imagineering Inc. I got 2 of a 4layer 30"sq for an into deal at $50 each.

Also see the assembly layer for that pcb as well as an example of mid-dense SMT/PTH pcb. I will have to generate a silk dwg.
Basically I turn on silk and soldermask, make sure no overlap as you do usually do not not want any ink on a hole to be soldered. Only the very good layout packages, not orcad layout even, have a clip silk option to remove silk SM overlap conditions. The pcb house usually does this for you if they are any good.
Text for silk, I usually standardize on 8 or 10 mil. Height down to say 50 with a 6 mil line.

Go to the pcb house that you plan on using an look at the design rule requirements and check that you meet them all for trouble free processing

Futurlec.com - Printed Circuit Boards - Technical Information
Futurlec.com - Printed Circuit Boards - Frequently Asked Questions

If you do not state what you want then you get the default processing.
Attached Files
File Type: pdf PORT MP3-TUNER-M1-REV A0-FAB DRAWING.pdf (67.7 KB, 18 views)
File Type: pdf TPA3100_section.pdf (166.0 KB, 13 views)

Last edited by rsavas; 31st December 2013 at 06:06 PM.
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