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how do you design a class d feedback network?
how do you design a class d feedback network?
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Old 27th August 2003, 03:52 PM   #1
Randy Knutson is offline Randy Knutson  United States
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Location: Willmar, Minnesota
Default how do you design a class d feedback network?


I'm also building my first class D audio amplifier but before I begin I was wondering if anyone could provide some advice or foresight to this project.

Here it goes:

I'm looking for a bandwidth of approximately 20khz and an output of around 500W RMS into an 8 ohm load.

I'm considering using the HIP4080 as my low and high side mosfet drivers. It has an onboard comparator and dead-time so I'm thinking all I need to do is put a 200khz triangle wave on the non-inverting side of the comparator and my level shifted audio on the inverting side. The HIP4080 will drive an h-bridge output with 3 mosfets in parallel on all 4 "corners" of the h-bridge. This bridge will feed a lowpass filter with an Fc of around 30khz.

As of now I'm a little confused with the design of the feedback network. From what i've seen i should use an opamp on the output (after the filter) to subtract the (+) and (-) of the signal out and feed this back to the comparator input??? I'm a little confused about this....

Thanks in advance!
Randy Knutson
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Old 27th August 2003, 06:32 PM   #2
jan.didden is offline jan.didden  Europe
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In my SONY TA-N88 the PWM signal itself is fed back to the right hand gate of the input differential fet amp stage.

BUT, there is a cap between this point and the collector of the PNP driven from the load resistor of the left hand input fet, that makes it an integrator.

So, it looks what you need to do is to integrate the PWM signal (for switching freqs at least) and use that signal as a conventional feedback signal to the analog input circuitry.

Jan Didden
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Old 27th August 2003, 07:24 PM   #3
phase_accurate is offline phase_accurate
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There are two places to look at:

1.) The respective HIP4080 application note.
2.) This tread: http://www.diyaudio.com/forums/showt...threadid=14847



P.S.: Take care about the IC's output-current capabilities when driving so many FETs in parallel !
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Old 30th August 2003, 06:00 AM   #4
DUG is offline DUG  Canada
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Location: mississauga ontario canada
Read the pdf ap-notes for the 4080 and its' evaluation kit ... there are at least 3

Calculate the combined gate charge required for your 3 FETs, the gate drive current output of the 4080, and the resultant turn-on time. You may find that 200kHz is too high.

I have a 2 layer board designed but have not moved this project up my list very far.

The feedback network is not the greatest hurdle, the output filter is!!
Doug We are all learning...we can all help
"You can't stop the signal, Mal. Everything goes somewhere..."
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