Simple Symetrical Amplifier

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Who said that ?
What you said about delay is true. But the problem does not fully rely on that. First Nyquist law will never let-you run an amplifier with a 180° phase shift if any gain ;-)
Second, delay matters with fast changes in the signal, right ? And delay will bring overshoot Agree ? Slew rate limitation and good compensation avoid that. So the real concern is just final slew rate of your amp and flat response with no overshoot..
Where the delay/phase problem is your is when you are working on poles optimization / harmonization.

exactly that was what i was trying to say/write. If you overcompensate the slewrate will be to long.
 
A time delay, IOW a latency (caused by long transmission lines or so) is mathematically expressed by: exp(-sT). It delays the arrival of signal at the receiving end by an amount equal to T without altering the amplitude. Thus the onset of the step response is also belayed by T seconds.

OTOH, a phase lag (caused by a LP filter or capacitances of a tranny etc) are expressed by e.g. (1-exp(-sT))/s, which does alter the amplitude, but it does NOT delay the onset of a step response or so.

If you call these crucial differences just semantics, you've missed my point (and fundamentals of FB theory).

Exactly as the big book says.
 
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Sounds like semantics to me. Whatever you choose to call it the voltage rise is delayed so there is a delay - even though it is called current feedback in fact the i/p transistor compares voltages. So if the voltage rise is delayed, there is a delay before the signal gets back to the feedback transistor. - end of story.

Edmond is right. The voltage rise (or fall) is not delayed. The voltage changes at the feedback immediately after a voltage change at the amp input (save a very small transit delay in the amp, which is irrelevant to this discussion).

Think about it. If you send a current into a cap, the cap voltage will immediately react to any current change. NO delay. There is a phase shift because the voltage across the cap is the intergral of the current into it. So, if you send a sine wave current into the cap, the result is the integral of a sine - which happens to be also a sine, but phase shifted.

On an amplitude vs freq curve it LOOKS as if the output sine is delayed wrt the input sine wave but that is ONLY because it just happens that the integral of a sine is also a sine.

If you do the same test with, say, a square wave or a triangle you will see that the output or the feedback node reacts IMMEDIATELY to changes in input voltage, so no delay, only a phase shift. And all this is precisely the reason that feedback actually works.


jan didden
 
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I agree with you about using CF because it is a fast topology and this sounds best but having chosen this topology I think it is best to avoid using too low value resistors in the FB circuit to try to speed things up even further - In my experience the opposite sounds better.

Do others have the same experience ?

Actually, there is a maximum resistor value you can use before instability sets in. That has to do with the (small) parasitic capacitance at the inverting input. Too large a feedback resistor causes phase shift leading to instability.
Most CF data sheets for instance warn against this and specify a maximum resistance value.
I am not aware of any minimum limit for those resistors, although at a certain point they start to load the output down too much of course.

jan didden
 
Thx for that feedback Jan,

When I switched feedback resistor values from 50R / 1K to 100R / 2K2 in my DC linked fetzilla the sound was significantly cleaner - I left the millar cap unchanged so stability was significantly increased.

I guess I must have been within the limits you describe.

cheers

mike
 
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Thx for that feedback Jan,

When I switched feedback resistor values from 50R / 1K to 100R / 2K2 in my DC linked fetzilla the sound was significantly cleaner - I left the millar cap unchanged so stability was significantly increased.

I guess I must have been within the limits you describe.

cheers

mike

Mike, I don't know the limits in your particular application, so you may well be right.

I just wanted to note that as far as stability is concerned, larger becomes worse.
In a CF opamp for instance, generally anything above 1k leads into danger territory.
They are so sensitive that the extra 4 or 5 pF of an opamp socket pin can ruin stability; those opamps should for best performance be soldered directly to the board, and layout should take care of minimum parasitic at the inverting input.
Same with power amps of course but I have no experience with the actual numbers involved there.

jan
 
When I switched feedback resistor values from 50R / 1K to 100R / 2K2 in my DC linked fetzilla the sound was significantly cleaner - I left the millar cap unchanged so stability was significantly increased.

May be if you listen at very high SPL you will hear worse sound? I don't understand why stability should have been automatically increased (unless you have measured it)

I think it is best to avoid using too low value resistors in the FB circuit to try to speed things up even further - In my experience the opposite sounds better. Do others have the same experience ?

I think I have heard people saying that lower resistance has lower noise. But I think there are more other critical things that are more important to consider when we talk about feedback resistors.

In my experience, there is no rule whether higher or lower resistance is better or worse. I prefer to say that there is that optimum value.

1) FB resistors affect stability (e.g. against capacitive load). More often you cannot go too high, but often you cannot go low either. There is an optimum.

2) In your DC linked (I assume this means you have no cap in the FB so RC is not affected) Fetzilla, by increasing FB resistors you hear cleaner sound. But don't forget that when you get lower THD at low SPL, you may get higher THD at high SPL, because oscillation always starts at certain high SPL. ADD: You have increased the FB by going from 1K/50 to 2K2/100 (instead of 2K/100), which most of the time will lower the THD (audible or not)

3) In a differential amp (opamp/LTP) I have heard there is a benefit from balancing the inverting and non-inverting entry points. This is too complex imo because there are many other things that are affected, most important (imo) is the input impedance of the amp itself. Yes, I have experimented with this, listening to various schemes, but I couldn't hear the benefit of "balancing" the differential amp/opamp this way.
 
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May be if you listen at very high SPL you will hear worse sound? I don't understand why stability should have been automatically increased (unless you have measured it)

I did measure both in spice & in reality, the test was 10khz sq waves with 8R & 1nF, the parameter I was observing was amplitude & duration of ringing. The results were consistent. With all else equal, if increasing FB impedance as mentioned above the slew rate becomes less along with the amplitude & duration of ringing.

This may seem insignificant or even a backwards step to some but subjectively the amp sounded significantly cleaner and more relaxed in it's presentation.


I think I have heard people saying that lower resistance has lower noise. But I think there are more other critical things that are more important to consider when we talk about feedback resistors.

agreed on both points

In my experience, there is no rule whether higher or lower resistance is better or worse. I prefer to say that there is that optimum value.

Also agreed - but I have yet to establish what this is, for now all I know is that 2k2 / 100 sounds much better than 1K / 50R


In your DC linked (I assume this means you have no cap in the FB so RC is not affected) Fetzilla, by increasing FB resistors you hear cleaner sound. But don't forget that when you get lower THD at low SPL, you may get higher THD at high SPL, because oscillation always starts at certain high SPL. ADD: You have increased the FB by going from 1K/50 to 2K2/100 (instead of 2K/100), which most of the time will lower the THD (audible or not)

It is clean at all SPL's - but before measures were taken the some low level oscillation occurred at mid SPL's.

Actually going from 1k/50 to 2k2/100 increases the CLG and thus decreases the FB but as you suspect this is not a significant difference.
 
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Edmond is right. The voltage rise (or fall) is not delayed. The voltage changes at the feedback immediately after a voltage change at the amp input (save a very small transit delay in the amp, which is irrelevant to this discussion).

The voltage rise is not delayed , that s right but the voltage at the
inverting input will continue to rise after the input signal has already
changed direction , the time it takes the inverting input to also
change its direction is of course dependant of the amp s slew rate.
 

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1) FB resistors affect stability (e.g. against capacitive load). More often you cannot go too high, but often you cannot go low either. There is an optimum..
Easy to understand: this cr resistance is too a charge for the first stage.
In my amp, 1K was the best compromise, considering bandwidth vs distortion/Peak level.
It is the same work we have to do at each pole, to find the optimized current.

My method is simple: In a correctly designed CF amp, it is stable with just a non compensated CR resistance. Sometimes, you just get a peak in the response curve at hight frequencies, just before the roll off. (too hight Q) . I just compensate CR for that and add a little filter in the input to flatten peaks in square waves.

If you overcompensate the slewrate will be to long.
Huim... Compensation speed-up high frequencies transmission in the cr, (= turn the phase, = increase the hf level). Slew-rate is just correlated with open loop bandwidth and will not change a lot.
 
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The voltage rise is not delayed , that s right but the voltage at the
inverting input will continue to rise after the input signal has already
changed direction , the time it takes the inverting input to also
change its direction is of course dependant of the amp s slew rate.

No it is not dependent on slew rate. You guys keep confusing slew rate with rise time and phase shift.

jan
 
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You should read more cautiously what i did write....
[snip

I did. You wrote:
The voltage rise is not delayed , that s right but the voltage at the inverting input will continue to rise after the input signal has already changed direction , the time it takes the inverting input to also
change its direction is of course dependant of the amp s slew rate.

It is not dependent on slew rate.

What is the parameter that define the time it takes for an amp to react to a change in the direction of the input signal ?...

No idea. If you mean the time it takes for an amp's output to react to any change in the input I'd say transit time. I think Edmond already showed that it would be in the nS range. Is that what you meant?

jan
 
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could you define each of them jan to clear the confusion ?

I already tried to explain phase shift.

Rise time is a small signal parameter. You may have an amplifier that, small signal, has a rise time of, say 5uS. So if you put in a fast square wave, low level, you'll see that the output square wave rises from low to high level in 10uS. Often the fall time is the same but not always. The rise time depends, roughly, on bandwidth and can indeed be used to measure things like BW, phase shift, indicate stability and such.

Slew rate is the maximum rate of change of a node in a circuit or, perhaps in this context, the amp output signal. It is a large-signal parameter and that is significant. If, in the above example of the 5uS rise time amp you increase level, you'll get to a point where the amp output can no longer keep up with the swing in voltage in that 5uS and the output starts to look like a linearly rising level. The cause is often that an internal compensation or device capacitance cannot be charged/discharged fast enough to keep up. For instance, an input stage with 1mA bias current feeding a Vas with a 100pF comp cap can only send 1mA into the 100pF maximum. 1mA into 100pF through C*dV=I*dT gives a max slew rate of 10^7V/Sec or as is more usually expressed 10V/uS. So if the output has to swing from -40 to +40V it will take at least 8uS independent of the rise time and bandwidth, and will look horribly distorted.

Hope this helps,

jan
 
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