Simple overview: it is all the time just about the symmetrical current feedback loop front end (pic) in all kind of variations.
So far two versions incorporating this topology were actually built and listened to, mine and Nico's. Time will bring out the best from the simple ones. But if someone wants to go to more complex design I would suggest post #205.
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Alex's board is nicer looking than mine so uses Alex's board. I just showed what I use for interest sake. My track are fairly narrow and pads are small which is not so great if you are going to etch at home, my PCBs are commercially made.
Alex what Salas said regarding 50/63V caps makes good sense if there are people who want to push the power envelope a little, all I wanted to do was confirm that the amp sounds as good as it is simple. It does.
Nico
Alex what Salas said regarding 50/63V caps makes good sense if there are people who want to push the power envelope a little, all I wanted to do was confirm that the amp sounds as good as it is simple. It does.
Nico
Today I made some measurements with the SSA BIGBT exact sch post #217
As you can see from the Tex scope plots, CH1 input signal, CH2 output signal:
- first plot, fs = 1 kHz, Av = +21,44 dB, phase shift = 0°
- second plot, fs = 2 MHz, Av = +21,68 dB, phase shift = -24°
I also measured/calculated the output impedance at 1, 10 and 100 kHz, 4 ohm load and it is 180 mohm in all cases, which will also be improved with higher voltage gain in the second stage, later in the process.
So I intend to prepare SSA sch, mosfet driver/BJT output, soon.
P.S. Input signal at 2 MHz is a little bit more rounded than at 1 kHz because of the signal generator upper limit distortion. As you can clearly see on the plots, output signal corectly followed this anomaly.
In the whole SSA amp there were no compensating capacitors whatsoever, only three electrolytic caps for DC potentials smoothing.
As you can see from the Tex scope plots, CH1 input signal, CH2 output signal:
- first plot, fs = 1 kHz, Av = +21,44 dB, phase shift = 0°
- second plot, fs = 2 MHz, Av = +21,68 dB, phase shift = -24°
I also measured/calculated the output impedance at 1, 10 and 100 kHz, 4 ohm load and it is 180 mohm in all cases, which will also be improved with higher voltage gain in the second stage, later in the process.
So I intend to prepare SSA sch, mosfet driver/BJT output, soon.
P.S. Input signal at 2 MHz is a little bit more rounded than at 1 kHz because of the signal generator upper limit distortion. As you can clearly see on the plots, output signal corectly followed this anomaly.
In the whole SSA amp there were no compensating capacitors whatsoever, only three electrolytic caps for DC potentials smoothing.
Attachments
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Salas, I adjusted the gain to work with my pre-amp out which is 2V p-p. I have not checked OLG, but the BW is huge so I cannot see a problem increasing gain a tad.
I have not decided what final bias should be, it sounds nice as it is. On the week-end I will set up the spectrum analyser and see what bias offers the best harmonic distribution. Just by listening it is hard/impossible to tell.
I have not decided what final bias should be, it sounds nice as it is. On the week-end I will set up the spectrum analyser and see what bias offers the best harmonic distribution. Just by listening it is hard/impossible to tell.
For the full power measurements I will prepare some 200VA transformer/60mF caps bank running on +/-35V, as specified as Safe Operating Area for one output pair in SSA.
Until now I have used 1,5A limited power supply for the safety reasons, like always at the begining of any new power amp's life.
I also calculated the propagation delay in the 2 MHz Tek plot from input to output waveform which is exactly 33ns, I suppose due to parasitic capacitances sumed from all semiconductor parts together and current layout (spider network). This figure maybe improved or not with the use of a neat PCB like Alex or Nico made, will find out later.
P.S. The propagation delay in 1kHz plot is of course the same 33ns, only that it is not visible in 500us/DIV time domain sweep.
Until now I have used 1,5A limited power supply for the safety reasons, like always at the begining of any new power amp's life.
I also calculated the propagation delay in the 2 MHz Tek plot from input to output waveform which is exactly 33ns, I suppose due to parasitic capacitances sumed from all semiconductor parts together and current layout (spider network). This figure maybe improved or not with the use of a neat PCB like Alex or Nico made, will find out later.
P.S. The propagation delay in 1kHz plot is of course the same 33ns, only that it is not visible in 500us/DIV time domain sweep.
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