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Old 27th June 2011, 03:57 PM   #1
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Default OLG Phase vs Output Phase

What is the relation between OLG phase and Output phase?

Doing some simulations of my amp and using the Audioamp.asc example in LTSpice shows the OLG and phase margin seen in the first picture, second picture shows output of my amp by AC analysis, with completely different phase and no phase margin whatsoever.

How important is the output phase, should there be some phase margin there as well?
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File Type: png Open loop gain.png (34.0 KB, 122 views)
File Type: png Output.png (23.9 KB, 121 views)
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Old 27th June 2011, 04:15 PM   #2
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Originally Posted by Neutrality View Post
What is the relation between OLG phase and Output phase?

Doing some simulations of my amp and using the Audioamp.asc example in LTSpice shows the OLG and phase margin seen in the first picture, second picture shows output of my amp by AC analysis, with completely different phase and no phase margin whatsoever.

How important is the output phase, should there be some phase margin there as well?
Are both open loop?

jan didden
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Old 27th June 2011, 04:17 PM   #3
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Originally Posted by janneman View Post
Are both open loop?

jan didden
No, the last one is just measuring the output of my amplifier using the AC Analysis in LTSpice. That should be closed loop.
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Old 27th June 2011, 04:39 PM   #4
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Now output without input filter.

Forgot to bypass it.
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Old 27th June 2011, 04:59 PM   #5
kevinkr is offline kevinkr  United States
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I think your compensation needs work, the CL phase margin appears to be non-existent at gains and phase shift well above that required for oscillation. You really want about 60 degrees of margin at the 0dB intercept closed loop.

Introducing a first order roll-off (dominant pole) in the VAS at a couple of hundred kHz might do it, but without seeing the design it is hard to know.
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Old 27th June 2011, 06:06 PM   #6
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Originally Posted by kevinkr View Post
I think your compensation needs work, the CL phase margin appears to be non-existent at gains and phase shift well above that required for oscillation. You really want about 60 degrees of margin at the 0dB intercept closed loop.

Introducing a first order roll-off (dominant pole) in the VAS at a couple of hundred kHz might do it, but without seeing the design it is hard to know.
This schematic.

Everything is ok and simulates well, with low distortion, just need to do some work on the CL phase margin and Im done. But it turns out to be quite hard and I really dont know what to do about it.
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Old 27th June 2011, 07:22 PM   #7
wahab is offline wahab  Algeria
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Your compensation network is undersized.
Increase C4 to 68pF, C8 to 270pf and R30 to 2.7K at least.
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Old 27th June 2011, 07:31 PM   #8
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Originally Posted by wahab View Post
Your compensation network is undersized.
Increase C4 to 68pF, C8 to 270pf and R30 to 2.7K at least.
Im afraid it is not so simple, been playing around with different values for hours with no good result, OLG remains more or less excellent through it all with a phase margin of more than 60 degrees at all times. But the CL response is just crap no matter what combination I try. Offcourse I *CAN* get a good phase margin bur really destroys my THD-20, at 72 Volts peak-peak(around 80 Watt) and crap CL phase margin I get 0.003xx% THD, but with good phase margin(atleast 60 degrees) which requires some rather high cap values I get 0.05xx%
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Old 27th June 2011, 07:39 PM   #9
wahab is offline wahab  Algeria
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Try BJTS as drivers, as using mosfets at this place doesnt bring anything,
and often, quite the contrary.
Test with either MJE15032/15033 pair or 2SA1837/2SC4793 pair.
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Old 27th June 2011, 07:44 PM   #10
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Originally Posted by wahab View Post
Try BJTS as drivers, as using mosfets at this place doesnt bring anything,
and often, quite the contrary.
Test with either MJE15032/15033 pair or 2SA1837/2SC4793 pair.
I wanted to isolate the VAS from the Output stage, hence the use of FET's as drivers.
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