"Load-invariant", LTspice and ringing

[Khron]

Greetings,

A couple years ago, i had started (and since, shelved) a pair of Douglas Self "Load-invariant" amps. For testing purposes, i had recreated it in LTspice, in an attempt to "flip" the small-signal stages (in order to tailor the design to the parts i had available). All that went well, biasing etc, i'm supposedly getting 0.003% THD@10k at full power, BUT...

While trying out Dr. Self's ideas about two-pole VAS compensation, i noticed there's a certain amount of ringing in the current through the Cdom (either in single-pole or two-pole), at the zero-crossings of the input/output. A tiny bit of that goes all the way to the output (visible on the plot). Seems to be around 2-2.4MHz...

The other day i searched for and found a simple way of plotting the open-loop gain (or at least a reasonable approximation for it) - adding "AC=1t" to the value of the feedback resistor (2.2k normally; ends up looking like "2.2k AC=1t"). This shows that i still have about 20dB of gain when the output phase reaches -180deg.

I used andy_c's models for the drivers and output pairs. I'm attaching the LTspice schematic.

1) Does anyone have any idea where the ringing's coming from, and how to curb it? The boards (self-made) just need a few more resistors and the semiconductors, and i'd like to get the design as ok as possible "in theory", to minimize later troubleshooting

2) By the looks of things, in the gain plot, there was a big zero with the OnSemi MJE15030/31 models (visibly flat plot ~100k-1meg), that got a lot less severe with the andy_c models. Where should i look, to curb some of that high-frequency gain?

Many thanks in advance,
Chris

[dadod]

Could you send LTspice files, with models?

[Khron]

Here they are: Blameless.asc = the schematic, and my standard.bjt with added models.

[dadod]

First, I don't like this circuit diagram.
Second, bias current was to low, I increased it to cca 180mA, check with Self description.
With normal Miller compensation distortion is to high, so I used TMC (C13, C15, R39).
Here is LTspice changed zip file. I think that you can get better result with more changes, but it needs time.
dado

[Khron]

Thanks for the mods Ok, loop gain seems to be ok now. But there's still that small burst of oscillation on the output, at the zero crossings (you'll have to zoom in to see it).

It's a lot more visible when you plot the current through the Miller capacitor(s)

[dadod]

Try 470pF between drivers base and collector. I did get less ringing 1-2MHz.
I think that this is comming from CFP output.
dado

[Khron]

I started with 470p, but 100p seems to have minimized that ringing. But i poked around the circuit a bit, and i'm attaching a zoom of the plot.

V(vout) is the output, after the R//L, V(n012) in red, is from the base of the upper driver (Q12, MJE15032), and V(n013) in grey, is from the base of the Vbe multiplier.

[dadod]

With double EF I don't get any ringing.
Maybe this is an artifack of the imperfect simulation??

[Khron]

Hmm, good point. That's always a possibility

But thanks anyway for the assistance so far

[cbdb]

The other day i searched for and found a simple way of plotting the open-loop gain

The way most of us do it is with the Middlebrook probe. Look for the example in the LTSpice educational folder.