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Old 15th August 2003, 02:12 AM   #31
jam is offline jam  United States
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Hi Charles,

I suppose attaching the drains to the output was a bad idea (Levinson used this topology with bipolars in some of their products) but what about the first two?

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Old 15th August 2003, 02:31 AM   #32
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Hello Jam -

I don't know too many Levinson topologies except for the one they stole from Sansui's 1981 AES paper on biasing class B output stages. But it still won't work as desired. Build it and see what kind of problems it has. It's such a simple circuit that you could breadboard it in 15 minutes. You'll learn a lot by doing so.

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Charles Hansen
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Old 15th August 2003, 12:10 PM   #33
Pedja is offline Pedja  Serbia
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Originally posted by jam
How about this
1) Add a trimpot across R2 to adjust for DC offset and remove coupling capacitor.
Trimming DC offset this way, you’ll also “trim” the bias through (and only through) J1. IMHO it is better to give up of the effort to get rid of the output cap.

Originally posted by jam
3) Attach fet drains to junction of output transistors and 100ohm resistors.
This probably will work, but what’s the goal?

Originally posted by Charles Hansen
You can't cascode the FETs, because they are followers.
Of course you can cascode the follower.

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Old 15th August 2003, 03:55 PM   #34
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Originally posted by Pedja

Of course you can cascode the follower.
Hello -

Maybe I'm being especially dense this morning, but I'm not sure how to cascode a follower. A cascode is defined as a common source stage driving a common grid stage (referring to FETs, of course), and normally works to keep a constant voltage across the first device. The main goal of a cascode is to eliminate the Miller capacitance to increase the bandwidth. I suppose one might be able to hook up a bootstrap around a follower to keep a constant voltage across it, and one might even call such a circuit a "cascode", but what exactly would be the point? (The source follower doesn't suffer from the Miller effect.)

Charles Hansen
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Old 15th August 2003, 04:44 PM   #35
SY is offline SY  United States
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I suppose one might be able to hook up a bootstrap around a follower to keep a constant voltage across it, and one might even call such a circuit a "cascode", but what exactly would be the point?
Charles, that's exactly what Nelson Pass called it in years past. IIRC, he abjured the use in an output stage, claiming that it restricted dynamics, or something like that. I'm not near my literature box and I'm no expert on SS, but theoretical advantages might be PS rejection and reduced Early effect.
"You tell me whar a man gits his corn pone, en I'll tell you what his 'pinions is."
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Old 15th August 2003, 05:07 PM   #36
jcx is online now jcx  United States
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Default Thanks Charles, everyone;

It looks like this is going in a better direction now.

Without the specific application context, we certainly can’t say if the buffer circuit topology under discussion is good enough or even remotely appropriate for the job but it certainly can be improved – in the sense of better measurable performance in areas we believe impact audible perceived performance.

I don’t know how to make my current source comment more clear, Q2,4 collector currents are set by the +,-Vcc1 to gnd voltages, any +,-Vcc1 variations with respect to gnd are reflected in the respective bias current source output current. Most high quality current sources use voltage references of some type to keep the output current independent of the supply, perhaps the designer has decided the effort he spent on regulating the supply means it can be considered perfect.

[sorry if some of this sounds repetitive now but I was busy, composed message before recent posts]

Cascoding is perhaps too specific a term, bootstrapping the input fet drains (which can be done with a “cascode” circuit) is my real suggestion here. This is commonly done in fet buffer circuits to boost the already high input impedance, other than electret/condenser mic buffers, there is little need for the available input impedance improvement with most audio sources. The indirect advantage that may be relevant is nearly eliminating the input transistor power variation and its properties’ thermal variations. Trying the numbers, you will find several degree C transistor die temp variation is likely without bootstrapping which can be responsible for mV level offset voltage modulation with low frequency audio signals – yes I know fets can be biased for a nominal 0 TC, and that there can be TC cancellation with the complementary input stage but I haven’t seen any audio designer explain that they have engineered in these cancellations and verified them over production ( consider different die sizes for n vs P fets, different Id to match Vgs or gfs or TC or 2nd order derivative matching; I don’t think your going to get them all)

The bipolar output stage buffer nonlinearities include Vbe modulation with output current and Hfe variation with output voltage and current as well as thermal modulations of these. A Pass style output cascode greatly reduces both the Early voltage component of the Hfe variation and the thermal modulation, selecting high voltage output transistors gives very flat Hfe with output current variation, linearizing the output transistor base current flowing in the fet source impedance. The complementary output with degeneration certainly seems be all that can done for Vbe modulation without feedback (unless something like Gilbert’s multi-tanh linearization or other cancellation scheme could be used) Some “no global feedback” people seem to accept the Sziklia feedback pair which can reduce the several percent distortion from the emitter follower to 0.1% levels and has high input impedance.

These effects are small, but so are the artifacts introduced by informed use of negative feedback, when did a “golden ear” audiophile ever accept an engineer’s argument that an effect was too small to be heard? (or that the minute problem du jour couldn’t be heard through the masking of say 3% SET amplifier or loudspeaker distortion)

As a precision instrumentation designer I do know where to find treatments of some of these analog design details scattered throughout the electronics and scientific literature but I seldom find audio design articles that convince me that many audio designers are using “error budget” analysis and certainly not extending the analysis into the dynamic domain to the state of the art - which has been moved forward in the last decade by ADSL and telecom chip designers who can offer -90 dB distortion from an op amp driving <50 Ohm loads at >1MHz Certainly we can’t expect to see much detail on this forum, but I would like to see some of the > 30 yr old audio design bromides so often set forth here reexamined, explained and/or updated in the literature
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Old 15th August 2003, 05:47 PM   #37
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Hello JCX,

I would agree with nearly all of your analysis from a technical standpoint. At the same time, my personal experience is that often the added complexity that results in improved measured performance will not result in improved audible performance. Now, I haven't tried everything, so it's certainly possible that I'm overlooking some potential gains. But that is why there are so many designers and so many designs out there. There isn't one "perfect" design (contrary to D. Self's apparent opinion).

One of my mentors (who posts here sometimes as jon marsh) would drive this point home to me very clearly when I was beginning in SS design. I would ask him "why did you do it this way?" or "why don't you do it that way?". His standard reply was "that's a valid approach, and it's not the one I've chosen. Why don't you build it up yourself and see how well it works?". Sound advice indeed!

And so maybe "cascoding" the output stage emitter followers would make an improvement, and maybe not. As SY pointed out, Nelson Pass used that approach in the past and has long since discarded it. Maybe it has some inherent problem. Or maybe NP just didn't implement it properly. The only way to find out is to spend a lot of time on the test bench building circuits, and a lot of time in the sound room evaluating them. My hat's off to anyone that spends the time to do both.

By the way, Ed Oxner of Siliconix has written a couple of excellent (but very hard to find) books on FETs. He walks through the steps to find the zero tempco point of a JFET (it doesn't work with all of them). I tried it with the Toshiba 2SJ103 and 2SK246, and it works extremely well. Bias them at 0.3 mA, and they are rock solid, both polarities. You can stick them on a curve tracer and hit them with either freeze spray or hot air, and the curve stays steady. Now 0.3 mA of bias has its own set of problems, so I never use this for audio stages, but it does come in handy for making current sources with a zero tempco.

Best regards,
Charles Hansen
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Old 15th August 2003, 10:10 PM   #38
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Well folks, I mostly agree with Charles, but jcox makes some very good points. Personally, I think that the ORIGINAL follower design is fundamentally wrong, because it does not naturally follow the characteristics of the devices used. This does not make it a bad design, or that it might even have some qualities that we might find important. Still, a comp j-fet driving a comp transistor output in a Darlington type configuration would work as well, and use less that 1/2 the parts.
The type of circuit originally posted works really well with all bipolar transistors. After all, it removes the need to add bias diodes, etc, to the input. When you use j-fets instead, you create a need to bias the j-fet which means adding led's. This is unnecessary, if you just invert the polarity of the fets and make a comp j-fet input follower driving a transistor pair. It can be done. Then the current sources are unnecessary, led's, etc.
For the record, many complementary j-fets have been made to match each other, especially with Gm. The trade-off is extra capacitance on the p-channel device. I hope that this helps.
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