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Old 29th April 2011, 03:35 AM   #1
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Default Parallel Output with Allison Bias?

Could something like this allow parallel outputs with Allison bias?
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Old 29th April 2011, 07:39 AM   #2
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I think so.
What shows your simulation?
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Old 29th April 2011, 11:53 AM   #3
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I get the same THD in simulation with one pair or two. My main motivation is the spread the thermal stress out across more devices. I have only ever done class B prior and the extra heat from class A is making me perhaps a little cautious. My simmed 1k THD>8ohm is 0.0000048 and my 20k THD>8 ohm is 0.000846, and it shows it can take an impedance dip to about 5 ohm. In the parallel version I think I'd maybe go with a little more current and do .62 RE just for a little added immunity to impedance variation.

I found it interesting that adding additional outputs in class B designs seems to really improve performance but didn't really change anything in the class A design.
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Old 29th April 2011, 12:04 PM   #4
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Good numbers.
Shows your circuit works well.
Adding parallell will improve THD. But you say not as much for Class A.
I think the main advantage comes near before to clipping. Not at 1 Watt.
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Old 29th April 2011, 12:14 PM   #5
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Those numbers were at 21.3V p-p into 8 ohm ~28W rms. I always work the design close to max output, I don't do the @ 1W thing to get better numbers.
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Old 29th April 2011, 12:31 PM   #6
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I see. Makes your sim values even better
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Old 29th April 2011, 02:28 PM   #7
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Do you change the emitter resistors when using singles (0.68=> 0.33)?
If so I think the results will not change much. MJL/NJL transistors have such a flat gain characteristic that whether they operate at 1A or 2A will not show so much difference.
I would only parallel them for higher powers.

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Old 29th April 2011, 09:01 PM   #8
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John, for the single pair of outputs I was using 0.33 for the emitter resistors. I suppose it makes sense now that you mention the relatively flat gain of these devices that there would be little difference in performance, I just hadn't thought of it.

My notion was to spread the dissipation amongst more silicon. I know the amp will have to dissipate the same amount of heat, I just thought it might be easier on the devices if each was required to dissipate less individually. Maybe the notion is mis-guided. In the end I just wanted to see if I was on the right track for paralleling devices with this type of bias scheme. No one has told me it will explode so it looks like it is worth exploring further. Thanks.
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