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Old 25th April 2011, 02:46 PM   #31
dadod is offline dadod  Croatia
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Quote:
Originally Posted by dadod View Post
Question for Hugh and OS!
You probably notice tha I use local feedback on VAS, that bridge over TMC(1meg//5pF).
It decreases open loop gain at low frequences from more then 100dB to litle less then 60dB and kip it up to 30kHz.
Some says that there is no benefit in it, but I coud not resist but to tray it.
What is you oppinion??
dado
I was listening this amp each day and the sound is so good that I think it is the best amp of all I made. I am not sure what part is doing good, the bootstrap CCS or constant OLG.
Next in my list I am going to bild, is similar amp but with two output pairs, capacitance multiplier and possibility to simple insert/remove local VAS feedback (rsistor//capacitor).
I am amazed how such simple amp could sound good. Bass is fantastic, and for mid and treble no complains whatsoever.
dado
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Old 25th April 2011, 02:55 PM   #32
dadod is offline dadod  Croatia
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Ops wrong schematic, this one is good
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Old 27th April 2011, 04:31 PM   #33
dadod is offline dadod  Croatia
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Some PCB errors corrected.
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Old 28th April 2011, 04:23 PM   #34
dadod is offline dadod  Croatia
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First PCB finished, laser printer and transfer method.
dado
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Old 1st May 2011, 03:21 PM   #35
AndrewT is offline AndrewT  Scotland
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Hi,
returning to the phase & gain plot in post1.

The phase margin @ ~2.3MHz is ~60degrees (gain = +0dB).
The phase margin @ 100kHz is ~ 25degrees (gain = +38dB).

How do these phase margins compare with an "unconditionally stable amplifier"?

Is that dip in phase margin around 100kHz, what is called "conditional stability"?
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Old 1st May 2011, 04:15 PM   #36
dadod is offline dadod  Croatia
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That phase dip at 100kHz is not stability problem.
dado
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Old 12th May 2011, 03:43 PM   #37
dadod is offline dadod  Croatia
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Progress.
I will test it first with lab power supply and then with proper one.
Here is populated PCB(almost).
dado
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Old 12th May 2011, 04:22 PM   #38
jcx is offline jcx  United States
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Quote:
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...
Is that dip in phase margin around 100kHz, what is called "conditional stability"?
yes higher order slope compensation schemes move towards the conditional stability region - but unless the phase margin dips below 0 then the loop doesn't actually support nonlinear oscillation

to oscillate you need to meet both the 180 degree phase shift and the gain = 1 conditions - Burr Brown's Graeme suggested calling it "gain stabilized" when the gain was large in the region of low phase margin

for tube amps it was a big problem because the gain slowly rises at turn on and sweeps the loop gain through the conditionally stable region

with solid state amps the gain is usually established within a small fraction of the potential conditionally (un)stable frequency

again to get oscillation you need both 0 phase margin and gain reduction to == 1

clipping is one way to get "gain reduction" - describing function analysis can be useful to us simple minded SISO "Classical" Bode theory based designers

the thing to look at is clipping recovery - the low phase margin at lower frequency may indicate ringing/sticking/poor recovery

when TPC, TMC component values are adjusted for the same loop gain as measured inside both loops, around the output Q then the stability/recovery behaviors look very similar


I have built composite op amp circuits with a region of 3rd order loop gain slope which do cross 0 phase margin at intermediate frequencies - if some of the gain comes from positive feedback involving the output stage then when the output stage clips the excess loop gain and phase shift both decrease on output clipping and the amp can be stable in clipping

slew rate limiting can also result in describing function gain reduction and some of my 3rd order loop gain protypes did have oscillations with slow slewing input op amps - not an issue with discrete design

Last edited by jcx; 12th May 2011 at 04:29 PM.
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Old 12th May 2011, 05:39 PM   #39
dadod is offline dadod  Croatia
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Thank you JCX for excellent explanation, I would not know to do that so good.
I did simulate with square wave and different capacitive load, and there was no ringing up to .2uF and with some up to 2uF.
dado
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Old 23rd May 2011, 09:52 AM   #40
dadod is offline dadod  Croatia
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Default first listening

I finished one chanell and power supply. I did same measurement of the bias current against temperature. I started with 20mV on 0.16ohm of the emiter resistor. As drivers are on separate heathsink, and bias spreader is on main heathsik together with output transistors, it settled its temperature faster. The bias current first increased to 25mV and then decreased to 19-20mV after output transistor reached cca 50 degree Celsius.
I could not resist but to connect it and did first listening.
I am very very pleased with result and I will come latter with more measuring and listenig when I finished second channel
dado
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