Lineup,
Here's my attempt at a schematic. The input device and VAS are the only suitable models I have; not too sure about voltage ratings.
However, I have adjusted input offset to achieve zero output offset, and set the quiescent to 125mA. You could go higher, of course. I have used a simple resistor to achieve this, rather than a Vbe multiplier.
I've added base stoppers, and used the 33pF lag comp you suggested.
Performance is not wonderful because loop gain is not high, will examine this later. Most of the distortion, however, is H2 and H3, starting around -60dB using +20dB as a reference.
Cheers,
Hugh
Here's my attempt at a schematic. The input device and VAS are the only suitable models I have; not too sure about voltage ratings.
However, I have adjusted input offset to achieve zero output offset, and set the quiescent to 125mA. You could go higher, of course. I have used a simple resistor to achieve this, rather than a Vbe multiplier.
I've added base stoppers, and used the 33pF lag comp you suggested.
Performance is not wonderful because loop gain is not high, will examine this later. Most of the distortion, however, is H2 and H3, starting around -60dB using +20dB as a reference.
Cheers,
Hugh
Attachments
Hugh
On the JLH SCA amp replacing the equivalent of R2 & P1 in your cct, with a current source worked wonders for performance - both in spice and in reality - I used that arrangement for a few years.
not sure if it would work here . . . but might be worth a try
mike
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I believe that the performance is vastly determined by the capacitance of the second stage fet.. hence my suggestion of keeping the Zetex fets with very low capacitance..and here with the limited voltage rails.. 10 mA for driving the output should be possible...Else resort to laterals...
The current could also be distributed through a current mirror..
The current could also be distributed through a current mirror..
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Lineup, all,
Thank you for your schematics and comments. I really like this design. It's almost like a FET JLH....well, I guess not, but as simple anyway.
As I mentioned in an earlier post I was working on something very similar with a BJT based input, but had not been able to get the bias/dc offset stable. Now I know why. I worked my way through lineup's schematic and thought about it and now have a better understanding of how it works. My problem was that I had not yet added feedback which cause the output to go to the rail with minimal bias/offset adjustment.
Now that I have added feedback I have managed to get it simming nicely in simetrix with 1A of bias. I'm definitely going to build this one using lineup's single jfet front end.
As I only need 10-20W of power I'm going to make a class A version...possibly with laterals.
Going to sim over the next day or two and try a few different layouts and VAS ccs topologies. I think I would prefer a bjt ccs for the VAS, as my (limited) experience has shown that BJT CCS's are more stable. If there's a good reason not to got this route, please enlighten me.
Will post back with a final proposed design for your perusal then order some parts. Will also look into lateral price and availability to help come up with the final design.
I'm very excited about this design. I really think it has the potential to quench my amplifier thirst for a while.
Thank you for your schematics and comments. I really like this design. It's almost like a FET JLH....well, I guess not, but as simple anyway.
As I mentioned in an earlier post I was working on something very similar with a BJT based input, but had not been able to get the bias/dc offset stable. Now I know why. I worked my way through lineup's schematic and thought about it and now have a better understanding of how it works. My problem was that I had not yet added feedback which cause the output to go to the rail with minimal bias/offset adjustment.
Now that I have added feedback I have managed to get it simming nicely in simetrix with 1A of bias. I'm definitely going to build this one using lineup's single jfet front end.
As I only need 10-20W of power I'm going to make a class A version...possibly with laterals.
Going to sim over the next day or two and try a few different layouts and VAS ccs topologies. I think I would prefer a bjt ccs for the VAS, as my (limited) experience has shown that BJT CCS's are more stable. If there's a good reason not to got this route, please enlighten me.
Will post back with a final proposed design for your perusal then order some parts. Will also look into lateral price and availability to help come up with the final design.
I'm very excited about this design. I really think it has the potential to quench my amplifier thirst for a while.
Mike,
Yes, makes a lot of sense, since it raises the loop gain almost an order of magnitude. This could be done easily but lag compensation would need to increase to preserve stability.
However, more feedback, while it reduces THD, smoothes FR and lowers output Z does create a longer spread of artefacts.
This circuit looks to have a loop gain of around 67dB, computed by examining the ratio of output to differential voltage across input and source of the input device.
I'm fairly sure small degeneration on the VAS would work well, but I'm limited in my models. You might note I've increased rail voltage for a bit more swing.
Cheers,
Hugh
Yes, makes a lot of sense, since it raises the loop gain almost an order of magnitude. This could be done easily but lag compensation would need to increase to preserve stability.
However, more feedback, while it reduces THD, smoothes FR and lowers output Z does create a longer spread of artefacts.
This circuit looks to have a loop gain of around 67dB, computed by examining the ratio of output to differential voltage across input and source of the input device.
I'm fairly sure small degeneration on the VAS would work well, but I'm limited in my models. You might note I've increased rail voltage for a bit more swing.
Cheers,
Hugh
Hugh,
Thanks for your schematic.
A few questions if you have the time:
1) What are the pros/cons of lineup's VBE/VGS multiplier versus the resistor you have used to set the bias? Also, what purpose does the parallel capacitor serve? Does using a fet based VGS multiplier provide better temperature stability?
2) What current are you running through your input jfet? I see you have used the same source resistor as lineup...does that value provide enough current for your chosen device?
3) Is the output zobel really required, especially if run in class A?
Your advice is appreciated!
Greg.
Hugh,
On my JHL I managed, even with the extra gain, with just about 30 - 50pF across the FB resistor - but I used some degeneration as well
In subsequent research on different designs I found splitting the compensation between FB resistor & gain transitor was an effective way of minimising the loss of OLG at high freqencies.
I guess this gives away that I'm true believer in the Church of High Feedback.
On my JHL I managed, even with the extra gain, with just about 30 - 50pF across the FB resistor - but I used some degeneration as well
In subsequent research on different designs I found splitting the compensation between FB resistor & gain transitor was an effective way of minimising the loss of OLG at high freqencies.
I guess this gives away that I'm true believer in the Church of High Feedback.
AKSA and others
My models in SPICE shows some better behavior.
One thing I found, too, is the harmonics are mostly H2 followed by some H3.
My models for latest schematic below:
swordfishy
THis latest schematic below is for Class A and laterals 2SK1058/2SJ162.
Shows THD 0.006% at 20 Watt. (Max is about 25 Watt with +/-25V supplyy)
Note especially H2 harmonics dominant. At rather high level.
I recommend you use those transistors for lateral amplifier.
Zetex ZVN3310A TO-92
Zetex ZVP3310A TO-92
And run second VAS stage with those at 5mA
with only resistors to set bias.
The latest schematic
Attachments
Farnell has laterals for audio, dont remember the brand, maybe magnatec or whatever. Ok in price.. and i'm not talking about the buz devices now.
irf240/9240 if I remember correctly does'nt match very good. not in rds'on and not in transconductance. I believe I use irfp9140 and 240. not perfekt but better imho. And the gates has to be driven MUCH harder on hexfet, I think I use arund 50ohms or so.
studies have shown that hexfet as vas may produce a wider spectrum of crap than bipolars, if that is what one want's, fine. I would'nt go for that, plus ther is a considerable a omount of gate capacitance.
plus one have to consider what happens when it gets warm, even when it's in a low current use.
I always try the amps shorted with a 1uF and 100n capacitor to ground and with different loads and at different biases. It's completly possible with irf's too.
and come on now, it's not hard to get like 0.000000001% thd numbers in spice.
With all that said, yes if this path you're going down now is done correctly, it should sound very very good in the end..(it only took me 10+ years to get there).
irf240/9240 if I remember correctly does'nt match very good. not in rds'on and not in transconductance. I believe I use irfp9140 and 240. not perfekt but better imho. And the gates has to be driven MUCH harder on hexfet, I think I use arund 50ohms or so.
studies have shown that hexfet as vas may produce a wider spectrum of crap than bipolars, if that is what one want's, fine. I would'nt go for that, plus ther is a considerable a omount of gate capacitance.
plus one have to consider what happens when it gets warm, even when it's in a low current use.
I always try the amps shorted with a 1uF and 100n capacitor to ground and with different loads and at different biases. It's completly possible with irf's too.
and come on now, it's not hard to get like 0.000000001% thd numbers in spice.
With all that said, yes if this path you're going down now is done correctly, it should sound very very good in the end..(it only took me 10+ years to get there).
MikelmHugh,
---
I guess this gives away that I'm true believer in the Church of High Feedback.
I am certainly one of that group, too.
But I do not like too many transistors. LIke to get as much gain as can be done with few transistors.
CCS constant current source is a friend of mine.
Did you download MultiSim 11?
As recommended by me in another topic.
This looks very nice. I like especially the feedback insertion (I'm a tube lover and it's mostly done like this way in tube amps). Although it is a pure voltage feedback in my opinion. The output voltage is divided and lies in series with input voltage (cause it is applied at the source of the jfet). Is there the possibility to apply the feedback at the gate of the jfet ? This would be parallel applied feedback (and this is the one I would call current feedback)
And another questiona bout the circuit in Post 29. If I want less Power cause of lower supply voltage, what do I have to change ? Only drain, source and feedback resistor of the jfet ? And if I use better mosfets (the zetex vor the driver and SEMELAB Laterals for the Power Amp) do I have to change anything in the bias topology ?
And another questiona bout the circuit in Post 29. If I want less Power cause of lower supply voltage, what do I have to change ? Only drain, source and feedback resistor of the jfet ? And if I use better mosfets (the zetex vor the driver and SEMELAB Laterals for the Power Amp) do I have to change anything in the bias topology ?
Lineup. What version of multisim are you using?
How did you import those models into multisim? Could you please discribe the process or give a link to the information you used to get the models to work in multisim?
I have had no problem with all the other spice programs I have used but importing models to multisim has got me beat... so far.
How did you import those models into multisim? Could you please discribe the process or give a link to the information you used to get the models to work in multisim?
I have had no problem with all the other spice programs I have used but importing models to multisim has got me beat... so far.
Me too, Mike, except I split the feedback..... nested and global.
Greg,
1. Very little sonically, except that Vbe multipliers tend to overcompensate bias creep with temperature on mosfet designs.
2. I'm using about 5.5mA, same as Lineup. The current through this device should be set however by R2/P1, rather than R4, so the jfet should be running well below Idss.
3. The output zobel ensures that the stage is loaded at very high frequencies, and it certainly provides additional stability for AB. In Class A, maybe no need, but frankly I'd want to build it and test it.
You can talk about these designs for eons, and people have, but it's a simple circuit, and while you can make educated guesses absolutely nothing beats building, measuring and listening to it!
Cheers,
Hugh
Greg,
1. Very little sonically, except that Vbe multipliers tend to overcompensate bias creep with temperature on mosfet designs.
2. I'm using about 5.5mA, same as Lineup. The current through this device should be set however by R2/P1, rather than R4, so the jfet should be running well below Idss.
3. The output zobel ensures that the stage is loaded at very high frequencies, and it certainly provides additional stability for AB. In Class A, maybe no need, but frankly I'd want to build it and test it.
You can talk about these designs for eons, and people have, but it's a simple circuit, and while you can make educated guesses absolutely nothing beats building, measuring and listening to it!
Cheers,
Hugh
Hugh,
Thanks for your answers. Good to know.
I have every intention of building it. Will order parts this weekend. Until then it seems silly not to optimise the design as much as possible with spice.
Lineup,
Would you mind simming the circuit with a J309 jfet front end and letting me know how it goes - if you have the model available and time to do it? This is the jfet I would like to use as it is easy to come by. You will need a much larger source resistor though.
If the J309 is no good, any through hole product that can be ordered from the fairchild website will do.
I have a model for the j309, but unfortunately not for the lateral output fets. Using vertical fets I have been unable to match your simulated figures, though they are still quite good.
Appreciate your help!
Greg.
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