JFET input, MOSFET VAS, LATERAL output = Perfect!! - Page 94 - diyAudio
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Old 11th June 2011, 02:13 AM   #931
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Increasing the feedback network impedance in order to use a smaller feedback cap will reduce OLG because the source of the Jfet will see a larger impedance, and lower it's effective transconductance.

Is it possible that a clever bootstrap can lower the load on the feedback cap so a smaller one can be used?

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Old 11th June 2011, 02:29 AM   #932
AKSA is offline AKSA  Australia
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Yes, Kean, I think it is possible. Alternatively we could lessen the load on the drain of the jfet by simply replacing the 1K VAS gate/rail resistor with a current source, that would raise OLG at least 6dB.

However, do we need MORE loop gain, or less, in light of SWF's preference for a more 'organic' sound?

I would suggest less..... but, heck, I was wrong once before in 1965!!

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Old 11th June 2011, 03:03 AM   #933
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I try not to make any direct suggestions, I just watch for what it is people want to do with the circuit and try to help them get there (although most often my help is not needed)... After all, I have no experience here.

So essentially, guys, I support your decisions, wherever they may go!

By default, I am with Hugh however, just for a failsafe.

I have one rogue idea though. Couldn't we replace all the current sources with bootstraps? After all, who can disagree with a passive current source? It is unlikely to be perfect, but I think it can be tweaked to as good or better performance than an active CCS using a trimmer and AC voltmeter (or scope).

I'll work on a schematic...

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Old 11th June 2011, 03:38 AM   #934
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Kean,

Most of my amps have bootstraps, except one, the Maya, so I tend to agree with you.

However, this is not our design, I defer to SWF who is doing all the heavy lifting and deserves credit, along with the redoubtable Lineout.

You remain the resident 17 year old genius on this forum, nothing can take that from you!

Hugh
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Old 11th June 2011, 04:05 AM   #935
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An LTSpice trick:

If you include this line:

.four {Freq} V(Vout)
.four {Freq} 4 V(Vout)

LTSpice will calculate the total THD twice: once computing all the harmonics, and secondly computing only the first 4 harmonics. The second number can be divided by the first to check for Hugh's 98% criteria. Note that if your circuit's noise floor is above the 4th harmonic, the distortion number will be wrong. A low noise floor is mandatory, so I recommend making the feedback and input caps 1 farad in simulation and this will correct most of the drift.

BTW, I have my simulation of this circuit ready.

Thanks for the compliment Hugh.

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Old 11th June 2011, 05:49 AM   #936
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Brilliant manipulation, Kean, many thanks. I've wanted a way to do this easily for some time!

Would you like to publish your sim results?

Hugh
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Old 11th June 2011, 06:12 AM   #937
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Hugh,

I managed to get some of the magic back. It's sounding quite good now. I upped the series feedback resistor to 500R again. I'm not sure if it is the reduced feedback or the extra voltage it requres across the input cap, but it sounds much better this way.

By the way, I was looking at the F5 schematic and I see Nelson Pass used 10R shunt resistors for the jfets - maybe 20R is on the money?
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Old 11th June 2011, 06:35 AM   #938
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If you want to lower the shunt feedback resistor substantially then I think you will want to worry more about the capacitor's parasitics and behavior. I wouldn't suggest going under 10R because the capacitor's self-resonance might become more pronounced. Why not try paralleling the cap with a 100n+10R snubber, so the HF impedance is less ambiguous? I think it is good practice to keep resistances larger than component inductances; this keeps reactivity and resonance reasonable and managed.

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Old 11th June 2011, 06:41 AM   #939
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I agree with you keantoken but I thought 1R would be sufficient with a 0.1uF to smooth out any tendency for ringing
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Old 11th June 2011, 07:09 AM   #940
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In the schematic attached the figure is over 99.9%, as long as you don't go over say 3A output. The output bias current affects this figure strongly; higher bias current decreases high order harmonics. Go to the miller cap and plot it's current. Now right click on the trace's name and enclose the label with D(). This will show you in a very visual and effective way the distortion which is causing this. I will try adding schottkeys to the MOSFET sources to see if I can increase non-switching behavior.

Mikelm, I defer to your wisdom since you know from experience.

PS, SWF, if you look at the current through the 20R VAS degen and the drain current of the CCS, I think you will find that most of the VAS current is consumed by the CCS, not the output transistors. I think using the BJT/MOSFET CCS would help to a great degree.

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