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Old 28th April 2011, 07:59 AM   #41
AKSA is offline AKSA  Australia
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Yes, the very last....

I shall do a LTSpice simulation just for fun......

Hugh
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Old 28th April 2011, 08:47 AM   #42
MiiB is offline MiiB  Denmark
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Lineup...

BUZ90x SPICE models

has the models
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Old 28th April 2011, 08:54 AM   #43
AKSA is offline AKSA  Australia
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Lineup,

Here's my attempt at a schematic. The input device and VAS are the only suitable models I have; not too sure about voltage ratings.

However, I have adjusted input offset to achieve zero output offset, and set the quiescent to 125mA. You could go higher, of course. I have used a simple resistor to achieve this, rather than a Vbe multiplier.

I've added base stoppers, and used the 33pF lag comp you suggested.

Performance is not wonderful because loop gain is not high, will examine this later. Most of the distortion, however, is H2 and H3, starting around -60dB using +20dB as a reference.

Cheers,

Hugh
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Old 28th April 2011, 09:04 AM   #44
mikelm is offline mikelm  England
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Quote:
Originally Posted by AKSA View Post
.

Performance is not wonderful because loop gain is not high
Hugh

On the JLH SCA amp replacing the equivalent of R2 & P1 in your cct, with a current source worked wonders for performance - both in spice and in reality - I used that arrangement for a few years.

not sure if it would work here . . . but might be worth a try

mike

Last edited by mikelm; 28th April 2011 at 09:05 AM. Reason: clarification
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Old 28th April 2011, 09:04 AM   #45
MiiB is offline MiiB  Denmark
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I believe that the performance is vastly determined by the capacitance of the second stage fet.. hence my suggestion of keeping the Zetex fets with very low capacitance..and here with the limited voltage rails.. 10 mA for driving the output should be possible...Else resort to laterals...

The current could also be distributed through a current mirror..

Last edited by MiiB; 28th April 2011 at 09:07 AM.
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Old 28th April 2011, 09:12 AM   #46
GregH2 is offline GregH2  Australia
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Lineup, all,

Thank you for your schematics and comments. I really like this design. It's almost like a FET JLH....well, I guess not, but as simple anyway.

As I mentioned in an earlier post I was working on something very similar with a BJT based input, but had not been able to get the bias/dc offset stable. Now I know why. I worked my way through lineup's schematic and thought about it and now have a better understanding of how it works. My problem was that I had not yet added feedback which cause the output to go to the rail with minimal bias/offset adjustment.

Now that I have added feedback I have managed to get it simming nicely in simetrix with 1A of bias. I'm definitely going to build this one using lineup's single jfet front end.

As I only need 10-20W of power I'm going to make a class A version...possibly with laterals.

Going to sim over the next day or two and try a few different layouts and VAS ccs topologies. I think I would prefer a bjt ccs for the VAS, as my (limited) experience has shown that BJT CCS's are more stable. If there's a good reason not to got this route, please enlighten me.

Will post back with a final proposed design for your perusal then order some parts. Will also look into lateral price and availability to help come up with the final design.

I'm very excited about this design. I really think it has the potential to quench my amplifier thirst for a while.
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Old 28th April 2011, 09:16 AM   #47
AKSA is offline AKSA  Australia
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Mike,

Yes, makes a lot of sense, since it raises the loop gain almost an order of magnitude. This could be done easily but lag compensation would need to increase to preserve stability.

However, more feedback, while it reduces THD, smoothes FR and lowers output Z does create a longer spread of artefacts.

This circuit looks to have a loop gain of around 67dB, computed by examining the ratio of output to differential voltage across input and source of the input device.

I'm fairly sure small degeneration on the VAS would work well, but I'm limited in my models. You might note I've increased rail voltage for a bit more swing.

Cheers,

Hugh
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Old 28th April 2011, 09:20 AM   #48
lineup is offline lineup  Sweden
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If you use laterals you can use one adjusted resistor for bias.
You also, which MiiB mention, use Zetex ZVN3310/ZVP3310 TO92 for VAS. Lower capacitance.
As laterals only need 5mA bias at the Gates, in VAS stage. Now is quite high for IRF240/9240 = 20mA
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Old 28th April 2011, 09:24 AM   #49
GregH2 is offline GregH2  Australia
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Quote:
Originally Posted by AKSA View Post
Lineup,

Here's my attempt at a schematic. The input device and VAS are the only suitable models I have; not too sure about voltage ratings.

However, I have adjusted input offset to achieve zero output offset, and set the quiescent to 125mA. You could go higher, of course. I have used a simple resistor to achieve this, rather than a Vbe multiplier.

I've added base stoppers, and used the 33pF lag comp you suggested.

Performance is not wonderful because loop gain is not high, will examine this later. Most of the distortion, however, is H2 and H3, starting around -60dB using +20dB as a reference.

Cheers,

Hugh

Hugh,

Thanks for your schematic.

A few questions if you have the time:

1) What are the pros/cons of lineup's VBE/VGS multiplier versus the resistor you have used to set the bias? Also, what purpose does the parallel capacitor serve? Does using a fet based VGS multiplier provide better temperature stability?

2) What current are you running through your input jfet? I see you have used the same source resistor as lineup...does that value provide enough current for your chosen device?


3) Is the output zobel really required, especially if run in class A?

Your advice is appreciated!

Greg.
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Old 28th April 2011, 10:09 AM   #50
mikelm is offline mikelm  England
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Hugh,

On my JHL I managed, even with the extra gain, with just about 30 - 50pF across the FB resistor - but I used some degeneration as well

In subsequent research on different designs I found splitting the compensation between FB resistor & gain transitor was an effective way of minimising the loss of OLG at high freqencies.

I guess this gives away that I'm true believer in the Church of High Feedback.

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