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Old 2nd May 2011, 12:40 PM   #111
GregH2 is offline GregH2  Australia
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Ok here is the semi final circuit (so far)

Sims at 0.007% THD at 10W and 20kHz. 10mA offset. And this is with the vertical output fets.
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Old 2nd May 2011, 12:42 PM   #112
lineup is offline lineup  Sweden
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Originally Posted by swordfishy View Post
Thanks Lineup. Does this mean the amplifier can't be direct coupled?

Edit: now I know what you mean. I need to disconnect the generator!
Even if your circuit does not need a cap
there will 90% sure be an output capacitor in what you connect to the input.
To keep gear from upsetting DC-offset it is good to put a cap on input of amplifier.
Not to would give a chance of upsetting DC-offset.
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Old 2nd May 2011, 12:45 PM   #113
GregH2 is offline GregH2  Australia
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Quote:
Originally Posted by WuYit View Post
swordfishy,
without thermal compensation you may lose those FETs within seconds. Current mirror can be a good thing when implemented "right". I personally prefer to keep the open-loop gain low.
Wuyit,

My (poor) understanding is that at the bias currents I will be running (1A) with the lateral output fets I will be using (don't mind the schematic, I don't have lateral models), the tempco is negative, and therefore an increase in temp will reduce current. Please correct me if I'm wrong.

You can read about the lateral fets I will be using in an earlier post in this thread.

As for the current mirror, you may be right. The amp seems quite unstable and needs a large miller cap for stability. I might try simming a few circuits with a simple resistive load. Reduced OLG might really help in this regard. I hate oscillation!

Will try a few simulations and report back.
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Old 2nd May 2011, 01:04 PM   #114
WuYit is offline WuYit  Sweden
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swordfishy,
now I have to apologize for not reading the thread.
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Old 2nd May 2011, 01:22 PM   #115
GregH2 is offline GregH2  Australia
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Wuyit,

Thank you for your updated schematic. I did a simulation and the amp was indeed more stable. I was able to drop the miller cap to 50pf. THD increased by an order of magnitude, but still very low.

Another problem created by dropping the mirror is that the DC offset is ruined by the assymetric current flow in the LTP, but I guess this could be rectified by a POT on the input.

Can you please explain the purpose of C4 and R12?

It's very difficult to know whether to use the mirror or not. So many pros and cons! I think at this stage, as BC560s are very cheap, I will try to stick with the mirror for now. Actually, I will build one of each type!

Thank you,

Greg.

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Old 2nd May 2011, 02:06 PM   #116
MiiB is offline MiiB  Denmark
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No sweat about the Fets.. They are laterals...so they will not run away...
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Old 2nd May 2011, 02:17 PM   #117
WuYit is offline WuYit  Sweden
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swordfishy,
C4 provides phase compensation (its value depends on dielectric as well). R12 reduces the power dissipation in T5.

Another possibility...
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Old 2nd May 2011, 03:03 PM   #118
MiiB is offline MiiB  Denmark
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WuYit...
why do you insert an extra driver stage..??
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Old 2nd May 2011, 07:17 PM   #119
MiiB is offline MiiB  Denmark
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ohh i see you use them for bias spreading....but does that carry any advantage compared to a simple resistor solution..???
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Old 2nd May 2011, 08:51 PM   #120
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hmm, this looks familiar.

If you change the VAS current mirror for a bootstrap cirucit in swordfish latest schematic, you have a spitting image of rod elliots P101 cirucuit.

I guess like minds travel the same path
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