JFET input, MOSFET VAS, LATERAL output = Perfect!!

[GregH2]

Lineup,

Thank you for your replies and help so far. It's looking good I think. I have added the input filter. Still trying to get the lateral models to work.

In the meantime I have been thinking that the VAS might be best made with a BD139 and BD140 (see below). The advantage of these over the ZVP3310 is that they can safely dissipate 0.5W without heatsinks which lets me increase the VAS current to 15mA.

I found that this configuration simmed worse than the fet CCS at 2kHz, but was better at 20kHz. The amp also seems a little bit more stable with the BJT VAS.

I have added C5 as per Hugh's schematic. This improved the THD at 20kHz too.

I have also added some current protection zeners which will be selected to limit the current to 10A or so.

One problem I have is that the simulated DC offset is now nearly 100mV. Any ideas for fixing that?

If you like I can send you the simetrix model of this amplifier.

Simetrix is a free simulator package for private use and comes with hundreds of models included. It can be downloaded from the simetrix website.

[lineup]

I understand.
With BD139/140 you are free to experiment with different current in VAS.
With laterals you need not more than 5mA VAS.

With IRFP240/9240 I think it is very good with at least 10mA VAS.
So, for IRFP240/9240 I have used IRF610/9610 MOSFET for VAS.
This allows higher current.

15mA would not hurt for laterals. But is not needed.

Simetrix I have not tried.
I will have a look at it.

DC-offset.
In this kind of input you should put emitter resistors in the mirror at top.
For 5mA each take 22 Ohm resistors.
Because drop should be 100-200mV across those.
In a real circuit without emitter resistors there can be temperature with offset.
This AKSA said in a topic.

Usually I put a suitable resistor across Q1+Emitter resistor to achieve near zero offset.
Can be a potentiometer.

[AndrewT]

Output offset is due to the choice of resistors around the input.
Q8 base sees 2k2 + [220p//47k] if the input is DC blocked.
Q9 base sees 11k.
They don't match !!!!!!

If the input is not blocked, then
Q8 base sees 4k4. Still not matched.

The input offset current must be low. Q8 & Q9 must be Cgrade and preferably matched for Vbe and approximately matched for hFE. The simulation will assume that the LTP is exactly matched for Vbe and for hFE.
Input resistance seen by the input currents must be almost exactly matched. A slight offset current can be compensated by a slight adjustment of base resistance to ground.

Power amps perform better if the "impedance" seen by the input is very low.
R13 prevents that low impedance of the 220pF being seen.
Try reducing R13 to 200r or somewhere <<1k0. Some designers adopt 0r0.
If you increase R15 then C6 can be made a bit higher, reducing the base impedance a bit more.

C2 (Cdom) is too high. Add in LTP emitter resistors to lower the gain of the front end.
Read Cordell. Or look at how many "good" designs always include emitter degeneration.
Add degeneration to the VAS as well.

[lineup]

Originally Posted by AndrewT

Output offset is due to the choice of resistors around the input.
Q8 base sees 2k2 + [220p//47k] if the input is DC blocked.
Q9 base sees 11k.
They don't match !!!!!!

yes, of course!

[lineup]

I show what your input could look like
when get zero DC-offset.
I added 10 Ohm emitter resistors to input pair
and 22 Ohm emitter resistors in mirror pair.

The main thing is that R9 and R10 are equal in value
because only those two gives base DC current to input pair.
Keeping them same value will give small DC-offset.

[WuYit]

hi,
my take on this:

[GregH2]

Lineup, Andrew,

Thanks for your help. I really appreciate it.

I added the degeneration to the mirror, LTP and VAS as you suggested. Simulated distortion doubled, but I guess it will help when the transistors are not equally matched (for the real life amplifier).

However, because of the reduced gain I was able to decrese the miller compensation cap which improved THD a bit.

Lineup, I tried changing the resistors on either side of the LTP to the values you suggested, but the offset went much higher! Instead, I tried decreasing the values of the feeback resistors which helped considerably. Only 3mV of offset now.

Also increased the input filter cap as Andrew suggested and dropped R13 to 200R.

Andrew, could you possibly explain how I determine the overall input impedence of the circuit?

Here is the current circuit. What do you think?

[lineup]

Put a capacitor 4.7u or 2.2uF at input after signal.
Because your generator with zero offset will fool you.
It puts current to the input base and KEEPS that side at 0V

Put cap in.
R6 should be equal to R3 47k
This makes R7 like 3.9k

[GregH2]

Thanks Lineup. Does this mean the amplifier can't be direct coupled?

Edit: now I know what you mean. I need to disconnect the generator!


Wuyit, thanks for your design. Can you please exaplain why you think it is better? I see you have removed the current mirror and used a Vbe multiplier for the bias. Is there anything else that makes it special?

[WuYit]

swordfishy,
without thermal compensation you may lose those FETs within seconds. Current mirror can be a good thing when implemented "right". I personally prefer to keep the open-loop gain low.