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Old 12th March 2011, 04:00 AM   #21
artu is offline artu  Chile
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Quote:
But will they sound fine?.... only building to listen and compare to a reference and test it using non biased evaluators.

Looks great..no doubts....but there's a lot of things that looks great but are not great.... sometimes sound ordinary as Hugh told.... well..he can say things about as he built.

regards,

Carlos
Only I should add that the 'unbiased evaluators' doesn't exists. Listening is always a 'biased process' that depends on many subjective and cultural background factors. Some will love sounds that are awful for others. And also it cannot be determined by vote what a 'good' sound is, maybe you can determine a 'popular sound', what the majority likes, and maybe that sound is not for me, so it is strictly personal.

Cheers
Arturo
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Old 12th March 2011, 04:28 AM   #22
artu is offline artu  Chile
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Quote:
Kenpeter :

OLG (voltage) is not increased by a source follower. Go figure...
And unfortunately neither is this specific example giving us any
current gain...

I agree about slew, thats why the driver stage is better here:
His output stage abusing same JFET at exactly same current.
Yet pulling SE against fixed CCS, is only half as capable as the
push-pull circuit that is driving it. Defeats its own purpose...
OH NO, the more loaded is the VAS the lower voltage swing will be (OLG), that's why the need of a buffer, expose the VAS to a light load and let the buffer do the brute force against the OPS. The output impedance of the buffer is determined by the EF (U1) not the CCS, you can replace the CCS by a resistor of 10K, 5K, 1K and the output impedance of the buffer will be almost the same, the only difference will be the quiescent current of the buffer, even more you can eliminate the CCS and the circuit will continue working. And yes there is a current gain with the buffer as it raises the output impedance of the VAS ... and so on backwards.

Cheers
Arturo
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Old 12th March 2011, 04:58 AM   #23
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Output impedance is overwhelmingly set by the closed loop, not by local impedance.
Source vs drain follower topology does not dictate how low the final number can be.
Available current swing runs out of steam twice as fast with the SF+CCS output.
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Old 12th March 2011, 03:57 PM   #24
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If the follower stage had been bigger than the driving stage,
all arguments for its necessity would have been reasonable.

But here is the sad truth we have been debating so far...
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Old 12th March 2011, 04:06 PM   #25
MiiB is offline MiiB  Denmark
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I am still i doubt, will it work with real not so perfect matched J-fets...how to keep the center from floating...??..
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Old 12th March 2011, 04:29 PM   #26
artu is offline artu  Chile
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Quote:
Kenpeter :

Output impedance is overwhelmingly set by the closed loop, not by local impedance.
Source vs drain follower topology does not dictate how low the final number can be.
Available current swing runs out of steam twice as fast with the SF+CCS output.
Yes an No, it is all about the amount of output distortion tolerable, among other factors. The more loaded VAS the more output distortion.

That's the controversy of direct VAS driving, EF2, or EF3 (depending on OPS devices), nevertheless you will need a minimum current gain (for a given load), regardless the FB loop, that is Ai>=Av(constant)*(Zi/Zo). So if you set the maximum distortion allowable, the minimum damping factor and the minimum input impedance for a fixed Av through the BW, it is very likely that a buffer stage will help the amp. performance. It is up to each concrete implementation.

Cheers
Arturo
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Old 12th March 2011, 04:38 PM   #27
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Originally Posted by MiiB View Post
I am still i doubt, will it work with real not so perfect matched J-fets...how to keep the center from floating...??..

Only thing I can think to randomize it more would be another JFET .model
I do have three or four slightly different .models for these same JFETs.

Offset maybe, but distortion don't look all that sensitive to mismatch...
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Old 12th March 2011, 04:53 PM   #28
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Arturo, if you had an EF3 OPS. Why add another EF buffer to make EF4?
Are we forgetting the OPS is already a buffer? How many stages can we
tolerate to be in a loop before layout starts to affect stability?
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Old 12th March 2011, 05:02 PM   #29
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And I might add something non-intuitive about closed loops.
All impedances inside a closed loop system are LOW.
Yeah, anywhere in the middle of the loop too.

Was so proud I had designed a Triode + PNP Concertina
phase splitter that was all DC coupled, had +/- 1/2Mu
voltage gains and absolutely equal output impedances.
Open loop, it made a huge improvement in symmetry.
But closed loop Williamson, it was no better or different
than plain phase splitter with unequal local impedances.
The loop drove both impedances to be absolutely equal.
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Old 12th March 2011, 07:00 PM   #30
artu is offline artu  Chile
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Quote:
Kenpeter :

Arturo, if you had an EF3 OPS. Why add another EF buffer to make EF4?
Are we forgetting the OPS is already a buffer? How many stages can we
tolerate to be in a loop before layout starts to affect stability?
The fewer EF's the better for stability, despite stability is a primordial concern there are other issues to take account, I understand that EFn includes de OPS as the last buffer, but it is not important to stick in a semantic issue. Including a buffer stage between VAS and OPS or not, is a trade off, what are average and peak current demands?, it's a 10W OPS or 16 device 2KW OPS?, the distortion?, stability?, BW? offset? ... etc. infinite solutions ... I am not advocating the use of more or less buffers a priori, it depends on the minimum that satisfy the rules of design, that are completely arbitrary because are 'my/your rules', if you achieve same or better results that full fills the 'rules' with no intermediate buffers, no doubt, that's a better design.

Cheers
Arturo
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