feedback from the plate V isn't linear - nonlinear feedback with a nonlinear gain mechanism isn't going to follow the rule for linear feedback around a nonlinear gain
how different does a cascoded triode look from one with high plate V excursion?
but I'd really rather people look at the Black Feedforward sim and tell me if it really works - I threw it together fairly quickly as my 1st attempt to understand "current dumping"
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how about discussing the thread topic
traversing the ~1.2 V dead zone in the unbiased bjt follower and the sudden gain change as the Class C Qs turn on is hard for negative feedback correct
the Black Feedforward scheme works very well in comparison - or has anybody looked yet?
a little bias still helps lots though - adding just 10mA bias to my sim resulted in sub ppm distortion for 240mA peak load current levels - not too bad
for those still interested in tube theory just try some search: Langmuir-Childs law
Improved vacuum tube models for SPICE, Part 1
basically the Vgc and Vgp voltages control the current via the same nonlinear law
traversing the ~1.2 V dead zone in the unbiased bjt follower and the sudden gain change as the Class C Qs turn on is hard for negative feedback correct
the Black Feedforward scheme works very well in comparison - or has anybody looked yet?
a little bias still helps lots though - adding just 10mA bias to my sim resulted in sub ppm distortion for 240mA peak load current levels - not too bad
for those still interested in tube theory just try some search: Langmuir-Childs law
Improved vacuum tube models for SPICE, Part 1
basically the Vgc and Vgp voltages control the current via the same nonlinear law
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Thanks for the investigation, JCX. Whilst "toobs" are just as valid for research, I got the impression that the OP was solid state. Would you care to look at this also from your perspective as your simulation has some interesting results. It seems it may also give an alternative direction to the current wave of EC interest.
I had a look at Black's feedforward but I would probably implement the floating load realisation rather than the paralleled output system. The main thing in my mind is to look at the performance when playing back low level signals as well, which means that as jcx you noticed that minimising inherent system errors is still a better method than just compensating for them.
As for my design in the OP, I really haven't done much to it aside from put a diode connected transistors between the inner outputs to reduce the biasing variation due to variations of the main biasing transistor.
I've transferred it to LTSpice to gain some better insight into usage with MOSFET's with this arrangement, unfortunately I'm still having issues with getting the various subcircuit models and libraries to load correctly.
As for my design in the OP, I really haven't done much to it aside from put a diode connected transistors between the inner outputs to reduce the biasing variation due to variations of the main biasing transistor.
I've transferred it to LTSpice to gain some better insight into usage with MOSFET's with this arrangement, unfortunately I'm still having issues with getting the various subcircuit models and libraries to load correctly.
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