How to calculate bypass cap across bias resistor?

[Henry8]

I'm using a resistor (110R) to set the bais for my single pair of lateral FETS (2sk1058/j162). The vas (mje340) is supplied by a ccs of around 11.6mA. How do i calculate the value for the ac bypass cap across the 110R bais resistor?

[AndrewT]

Good question.
I hope I find it in Cordell's book.

[Nico Ras]

What works in practice is C=(2 x PI x R x F)^-1 where F is the lowest frequency you want to pass, example 20Hz. For R = 110 Ohm it is 72.3 uF, next size up is 80uF.

[Henry8]

wow, i was going to try 0.1 to 2.2uF, as this is what i have seen on circuits that used a Vbe multiplier transistor. Thanks for the info.

[BobEllis]

Nico, That's the formula for an RC filter. In this case we are talking about a resistor in parallel with a cap.

I would look at this like a shelving filter - the R//C into the load represented by the Gate of the driven mosfet in parallel with the impedance to the rails. The Gate impedance is likely very high, so almost any capacitor will do to bypass a 110R resistor and not significantly impact the HF response. We use 100-200R as gate stoppers, right?

Practically, a few uf should be fine - 1uf film and/or a small electrolytic. 100 uf wouldn't hurt, but would possibly create a delay starting the mosfets with time constant set by the resistors feeding it. A couple uf would take a lot less time to charge up.

Disclaimer - I am not an electrical engineer, I would like to go through Bob Cordell's book but don't have it yet.

[nigelwright7557]

Originally Posted by Henry8

wow, i was going to try 0.1 to 2.2uF, as this is what i have seen on circuits that used a Vbe multiplier transistor. Thanks for the info.

The formula given is correct although I am not convinced you need a capacitor at all. After all the voltage across the bias should really be constant. If its not then you need a Vbe multiplier otherwise you might start cooking or under biasing the MOSFETs.

[Henry8]

Originally Posted by nigelwright7557

I am not convinced you need a capacitor at all. After all the voltage across the bias should really be constant.

The theory is that one fet is fed the signal directly, the other thru the bias R, so the cap is to ensure both fets see the same signal. Bias voltage variation is not the issue here.

[Henry8]

i guess no one knows.....................

[djoffe]

Depending upon the rest of your topology, the effects of the cap range from almost non-existent to perhaps medium significance. I'm imagining more facts than are currently in evidence...so I'll state my assumption.

Cdom wraps around the Vas transistor, to the low side of the 110 Ohm resistor. That defines the forward gain of the VAS to the low side of the 110 Ohms. If the Vas has a small emitter resistor, say 10 Ohms or less, the Vas will have a high frequency output impedance of about 10 Ohms. That says the bottom FET is driven by 10 Ohms, and the top FET sees 120 Ohms at high frequencies. Whether this matters depends upon the capacitive loading seen, and the bandwidth of your amp. Capacitive load depends on the output fets, and whether they have emitter follower drivers...

The main reason to include such a cap is to make the high frequency characteristics of the amp more similar between the push and pull sides.

[Henry8]

Thanks for your reply, djoffe.

My bmp file is 800k, cant upload now.... (not sure how to reduce it!)

Basically the amp is a 3 stager, pnp ltp input, a single bjt CE mode vas, with the fets driven directly from the vas collector.
The vas is supplied from a CCS.
The Vas emmiter resistor is 39R
The bandwidth is 50KHz
There is no miller cap, instead a r-c lag network is used instead.