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 buzz1167 6th September 2010 09:15 AM

Combined Topology - Thoughts?

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I've been looking around at different topologies trying to figure out as much as I can and I think I've figured out a few things, but I'd like to hear what you guys all think about it.

I've done some distortion searching using Doug's information and the ESP web pages.

I changed up the standard input stage a bit and here's why/how...

Firstly,
I reduced the Current Mirror Emitter resistors because 94mV seems to be sufficient to account for changes in Vbe that I've seen while building my test amps. I think I might even try to go further down to 22R's for reasons I state below, if I think I can get away with it without any Vbe problems.

Secondly,
Also I added a current mirror buffer because if I assume that the transistors have a Beta of about 200. 2ma output requires 10ua of base current. Since one side has both bases on it, I can expect to loose 20ua from side to side. That gives me a 1% delta right off the start.

Using Doug's articles as a guideline, a 2% difference in current matching equates to an increase from .1% to .16%THD which is huge!:eek: Using a single buffer, now the lost current equates to almost nothing. 20ua/200 = 100nA or .005% delta. That's gotta be close enough, right?

I've made an easy check on the VAS which I think is important.

Shown by Doug Self, Emitter resistance on the current mirror can bring out VAS distortion thus I thought it very important to keep Current Mirror Emitter resistors low and the size of Cdom Small (obviously). But also I think I have found my previous problem. I forgot to look at the VAS Transistor capacitance and its base resistor pull down.

I presume that the first amp I built with "Interesting" VAS transistors had it's problem with this value and I just didn't know what was happening.

Finally, the Driver Stage.

I know that typically there is a resistor/Capacitor between the drivers to cause the output base currents to evacuate more quickly and thus speedup turn off times. Using the capacitor just creates less impedance with increasing frequency, thus at some frequency, I assume it will cause IMD by shorting the output bases to each other thus eliminating the bias all together. Thus this seems like a band-aid rather than a fix, if you ask me.

However, I have recently seen the "Mongrel" amplifier which seems to have fixed this problem with a simple solution, CCS's on the output bases allows them to be shut off while not producing the zero impedance issues.

In my design I don't claim to even try to push enough current through the CCS's to bias the drivers into Class A, because I personally think that as long as they exist they will turn off the drivers as needed. Mainly they will push the drivers class B switch off point slightly away from 0V on the input signal, or to say it a different way, the drivers will be forced into class AB territory while the outputs can be biased independently.

I think this really buys you the fact that now your drivers and outputs don't have to be turned off simultaneously, the outputs will be turned off naturally on the way down using the CCS and the drivers will be left with the nasty/slower turn off effects. But since the drivers are now separated from the output signal it doesn't really matter does it? The question is really, just how much current do we need to ensure that those outputs get turned off effectively?

6ma has a slew limited frequency of 10mhz with my 600pf output drivers, maybe thats not high enough... I dunno. 1.2V bias and the 200R typ. resistor make about 6ma, that's my entire reason for choosing that value.

Any Comments on my Analysis or Circuit? I hope so!

 AndrewT 6th September 2010 09:50 AM

Quote:
 Originally Posted by buzz1167 (http://www.diyaudio.com/forums/solid-state/173130-combined-topology-post2294710.html#post2294710) Also I added a current mirror buffer because if I assume that the transistors have a Beta of about 200. 2ma output requires 10ua of base current. Since one side has both bases on it, I can expect to loose 20ua from side to side. That gives me a 1% delta right off the start.
I thought that too for far too long.
GK put me right.
It's down to setting up the VAS base current to exactly equal the sum of the mirror base currents.
Then the mirror is accurately balanced if the components are carefully matched as a full set, resistors, mirror transistors, VAS transistor.

The diamond arrangement driver is more usually used for small currents not as poweramp drivers.
What about looking for corroboration that either drivers be inserted between diamond and output devices or your chosen 6mA bias for drivers.

The extra resistor that D.Self uses is inserted into your Vbe multiplier. But the tapping to feed the drivers is taken from the wrong end of the extra resistor.

 lineup 6th September 2010 10:15 AM

Think you have done a good job.
Looks very good.

Some minor points I notice:

A) The 10k resistor to the base of input.
It is too high value.
Try 1k or 2k2. This is more normal.

B) The cap 47uF across VBE-multiplier.
Think this is way to high value.
My simulations show 1uF or 2.2uF.
1 uF is commonly used as far as I have seen.

C) Input mirror at bottom.
The transistor in between works at only base currents.
Try one 1k-2k2 resistor from the emitter to V-
It is from the junction of the two bases and emitter of middle transistor.
I have tested this type of mirror in SPICE
and at several occations were lowest distortion with ~1.8k resistor.
Makes this transistor work at like 0.400 mA

 homemodder 6th September 2010 10:57 AM

Quote:
 Originally Posted by lineup (http://www.diyaudio.com/forums/solid-state/173130-combined-topology-post2294741.html#post2294741) Think you have done a good job. B) The cap 47uF across VBE-multiplier. Think this is way to high value. My simulations show 1uF or 2.2uF. 1 uF is commonly used as far as I have seen.
Lineup if you do some stability plots with regards to the biasing circuit youll see why a higher value is actually better to ensure bias circuit stabilty, then have a look at some good, better than average commercial designs and see how their designers go it right. I wouldnt go below 10 uf and higher is better especially if youre using low esr type caps which have better sound quality.

 buzz1167 6th September 2010 11:20 AM

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Awesome input! I've made some changes.
The driver input on the wrong side of Vbe was just an error.

Maybe I'm just tired, but what is a "Diamond Arrangement Driver"? Did I draw one of those?

The pull down resistor on the current mirror seems to be in question, I can see where andrew is coming from because I briefly thought about the vas current. But I assumed (without checking) that the EF setup on the Vas would sink almost no current because of the ridiculous gain. Its gonna be on the order of 200^2.

Ok so I'm gonna try to go through it. I think that the steady state (No signal) is very close to when the VAS is pulling 6ma (the entire current source). Thus there is no current left for the drivers and the state of the the output is nominal, just bias alone. I hope I'm not being stupid here...

Now using a gain of 200 for the vas transistors I get a gain of 40,000 total from input to Vas output. For 6ma/40,000 = 150na. Which is awesome since the other side is loosing 100na to the buffer. Which means my offset is actually closer to 0 than I thought, but only by happenstance. :D I'm ok with that...

To make it academic, I need another 50ua from the current mirror, so lets try that resistor...
Using the idea for the resistor on the current mirror, lets see where we get. I need 150na from the base of the buffer to cancel the 150na going to the VAS, so that's 150na*200= 30ua at the common base. 20ua is being used by the transistors, so I need to shunt another 10ua to V-. Assuming .6V Vbe and the 94mV across the emitters I get .694V and thus to get 10ua I come up with 70k?

I like the idea of having a resistor there, if only for peace of mind that the buffer has a standing current no matter the state of the mirrors... But I cant get to the 2k number, Maybe I'm missing something that is just empirical?

As far as the 47uF Cap across the Bias, its specified in Doug's work and the Mongrel has a 10uF there, so I don't think I'm sooo off base. But to be honest I don't really know what its for...
I assume to keep the bias voltage constant? Wouldn't bigger be better for that use?
I get confused sometimes in the uses of capacitors, like this one. I know at 20khz its got almost no impedance, but... Ehh, my head hurts. :confused:
Maybe I'm just tired, I'm going to sleep...

Thanks guys! Keep the bullets coming :p

 AndrewT 6th September 2010 11:35 AM

Hi,
that 68k can be implemented with or without the third mirror transistor.

Look at the VAS and EF separately.

The VAS passes 6mA of Iq. Ic varies from an extreme of 0mA to ~2 to 3times Iq.
Lets say that is a range of 0 to 18mA.
Using hFE for that range of Ic, what is the range of base current and Ibquiescent?

Now look at the EF.
It passes the 1k0 resistor current and the Ib of the VAS. ~0.6mA + Ib.
If Ib varies between 0mA and 18mA/100 that gives an Ic range of 600uA to 780uA. What is the EF base current? Let's try hFE of 200.
Ib ranges between 3 & 3.9uA, if the amplifier does not approach clipping non-linearities. 6mA / 200^2 predicts Ib=0.15uA, That's why I said forget it.
You can add a trimmer (~5k to 10k) in parallel with 1k0 to set the EF base current and that in turn can tune the LTP currents to exactly the same value at quiescent conditions. Measuring Vdiff across the LTP emitters, confirms balance, if the 4 resistors are matched as very accurate pairs, <0.1%.

You don't need a simulator to work through this, but, you must understand this to be able to use a simulator and enable you to check you have asked the simulator the right questions.

 lineup 6th September 2010 12:23 PM

Quote:
 Originally Posted by buzz1167 (http://www.diyaudio.com/forums/solid-state/173130-combined-topology-post2294774.html#post2294774) To make it academic, I need another 50ua from the current mirror, so lets try that resistor... Using the idea for the resistor on the current mirror, lets see where we get. I need 150na from the base of the buffer to cancel the 150na going to the VAS, so that's 150na*200= 30ua at the common base. 20ua is being used by the transistors, so I need to shunt another 10ua to V-. Assuming .6V Vbe and the 94mV across the emitters I get .694V and thus to get 10ua I come up with 70k? I like the idea of having a resistor there, if only for peace of mind that the buffer has a standing current no matter the state of the mirrors... But I cant get to the 2k number, Maybe I'm missing something that is just empirical? As far as the 47uF Cap across the Bias, its specified in Doug's work and the Mongrel has a 10uF there, so I don't think I'm sooo off base. But to be honest I don't really know what its for... I assume to keep the bias voltage constant? Wouldn't bigger be better for that use?
Some uA more or less, it is not important.
When the currents sum up perfectly, does not say it is best performance.
Same with myself.
I can calculate this and that, but when I test i SPICE
I see that the teoretically perfect is not always the best.

When I say 1k - 2.2k for to set around 0.3 to 0.7 mA in that mirror transistor
it is based on many cases where I have run simulations on such mirrors.
Testing resistor after resistor and Fourier analys.
Then pick the resistor that gives lowest dist at 1 kHz.

I am not sure of the value you should use.
Because for a mirror 0.2 mA + 0.2 mA, then 1k8 was the best giving around 0.4 mA in T.
My guess is the resistor should set a current that is at somewhat same level as the mirror current.
--------

The 47uF.
Are you sure Doug has used?
But across drivers emitter resistor (often like 300 Ohm beteen NPN-PNP driver EMITTERS) there can be one 47uF, to suck out current from power transistors.
Colud you maybe think of this?

Again, when I recommend 1uF (or 2.2uF) it is because I have tested it in sim.
I also thought higher value would be better - but this was not the case.
I have seen quite many amplifiers where cap is at 1uF level.
This cap has such little effect,
that we can omit it.
Leave it out wont change hardly anything for the worse.
It does not do much good.

 lineup 6th September 2010 01:10 PM

1 Attachment(s)
Here is one case, where I tested 3 different MIRRORS.
Just like your amp, the VAS is a Darlington
and the output from input stage is at 1.26V = 2x0.63V drop

All 3 mirrors gave best result when VCE of U12 and U13 pair was EQUAL.
To do this I adjusted value of resistors R1 and R3.

Mirror1 and Mirror2, from the left, gave best and same result.
Mirror3, the type you are using, gave a tiny, tiny bit more dist.
I also tested 'your' Mirror3 without the 1.8k resistor.
Result got a bit worse.
Code:

```THD Distortion 16 Watt RMS into 4 Ohm: Mirror1, 0.000265% Mirror2, 0.000265% Mirror3, 0.000271% (with R15=1.8k) Mirror3, 0.000304% (without R15)```
Such small differences, I say, wouldnt matter nothing in real life.
There are plenty of things that would effect far more.
Which means that we can pick any sort of mirror
as long as we set it up in a good way = optimal.

 homemodder 6th September 2010 01:57 PM

Quote:
 Originally Posted by lineup (http://www.diyaudio.com/forums/solid-state/173130-combined-topology-post2294809.html#post2294809) The 47uF. Are you sure Doug has used? But across drivers emitter resistor (often like 300 Ohm beteen NPN-PNP driver EMITTERS) there can be one 47uF, to suck out current from power transistors. Colud you maybe think of this? Again, when I recommend 1uF (or 2.2uF) it is because I have tested it in sim. I also thought higher value would be better - but this was not the case. I have seen quite many amplifiers where cap is at 1uF level. This cap has such little effect, that we can omit it. Leave it out wont change hardly anything for the worse. It does not do much good.
Doug has it right too, higher value is better, do the theory correctly. This cap does have an effect not only technically but also in sound quality, just ask any experienced designer of high quality amps.

Omit it at your peril, real amps are quite different to simulated amps although you can get an idea why that cap is very much neccesary and you wouldnt find a design not using it, a good design in any case. When using better output stages like triples and you skimping on this aspect you might just find the reason you cannot get it stable, sorry no sim is going to show you whats happening.

A 47uf suckout cap ?????, hey Lineup whats up ???? Are you delibertly supplying incorrect info??? Why would you ever need such a high value ???? Please explain.

 AndrewT 6th September 2010 02:03 PM

Quote:
 Originally Posted by lineup (http://www.diyaudio.com/forums/solid-state/173130-combined-topology-post2294843.html#post2294843) All 3 mirrors gave best result when VCE of U12 and U13 pair was EQUAL. To do this I adjusted value of resistors R1 and R3. Mirror1 and Mirror2, from the left, gave best and same result. Mirror3, the type you are using, gave a tiny, tiny bit more dist. I also tested 'your' Mirror3 without the 1.8k resistor. Result got a bit worse.
mirror 3 is set up wrongly, if you ignore the extra resistor and transistor in the mirror.
The I1=0.4mA must equal the IbVAS + Ir2, since the same transistor is used for the EF and for the mirror.
Ir2~0.6V/330ohms

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