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Old 6th September 2010, 02:46 PM   #11
AndrewT is online now AndrewT  Scotland
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I missed the edit window.

If one then adds the extra resistor and/or the extra transistor then the current balance must be maintained.
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Old 6th September 2010, 03:42 PM   #12
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Why two separate 6mA CCS on driver emitters?
You will always have fixed voltage span between.
A single resistor of 220ohms would do the same.

------------

Also consider Shottky diodes in place of 0.1R in
the output totem. No combination of emitters
and resistors has square law curvature ideal for
AB crossing. Shottkys do.

Don't worry output quiescent without 0.1 resistors.
Talking stack of 4 Shottkys, technically a class B.
But you are really riding AB diode curves, smooth
and identical compliments. Diode drops so little,
TO220 Shottky never gets hot in this application.

MBR745 reasonable test subject for starters.

Last edited by kenpeter; 6th September 2010 at 03:58 PM.
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Old 6th September 2010, 06:07 PM   #13
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Kenpeter... Its an interesting argument you bring up, one that should be thought about.

The goal of the Overall VBias is obviously to stay constant barring thermal compensation, so one would think that the Vbias after the drivers would have a similar fate? Well from inspection, it looks like the 100ohm driver base could cause an issue with varying current and thus voltage at the base, based on the transistors nonlinear output/input. However in practice I've also measured that this voltage across the outputs is not constant, especially not using a typical .22uf speedup cap there (at least not for me).

If I think hard enough I might find another reason to do it the CCS way. Possibly because it fixes the driver steady state current which is no longer dependent on any voltages staying constant at the output bases (or not). Now if we think about that, what happens?

If the output transistors are pulled low by a current source then all we must say for the output bias current is that the driver output current is equal to Current source current + Desired Output Bias Current/Beta. This seems a simple enough task, right?

Thus the voltage across the output pair has disappeared from the equation for output bias currents!!!! Am I being stupid? It will be set according to the aforementioned currents at whatever voltage level works out, because we no longer enforce a 1.2V drop between the NPN and the PNP output transistor, they are separated as needed by the CCS's. Now let me see what I can gather from that.

I believe this means that we can now stabilize the output stage using only the drivers and the bias on a separate heat sink. And possibly if the bias currents are chosen well and the drivers are appropriately oversized, we might get rid of the need for thermal compensation!
This might also be an argument for running more or less current though the drivers:
1) One could think, less current!, because you could have hopes of keeping the drivers cool all the time, which might prove fruitful for low power amps or high beta outputs
2) Or one could exclaim, more current!, in the hopes of keeping an external heatsink closer to the same temperature under no load and load and thus relying less on thermal compensation.

Am I being crazy here or does this actually work?


Current Mirrors
I haven't ignored the current mirror argument, I just haven't sat down and came up with a solution. I am perplexed at the size of some of the emitter resistors i see though, why so big? In Doug Self's article, he admittedly "over degenerates" the input current mirror to show the VAS distortions, except that he "over degenerates" them with 100ohm resistors, AHH! Does this not mean havoc for your VAS running resistors on an order of magnitude higher? Maybe the EF stage is just very tolerant...

I post figures from his online article below only because I haven't yet grasped the issue. A picture of a test setup, a picture of the multiple Vas options - of which he proceeds to test the Cascode version, and Finally a picture of the emitter degeneration effects on a Cascode.
Attached Images
File Type: jpg self_ch18_fig3t.jpg (22.8 KB, 115 views)
File Type: jpg self_ch18_fig4t.jpg (19.2 KB, 113 views)
File Type: jpg self_ch18_fig6t.jpg (28.6 KB, 86 views)

Last edited by buzz1167; 6th September 2010 at 06:20 PM.
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Old 6th September 2010, 07:54 PM   #14
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I figured out that I had missed something on the current mirror check I did last night, I must have just been tired because it seems obvious now.

Picture posed below.
Assume 2ma through both sides of the current mirror. (perfect symmetry)
Assume 6ma through the VAS (output zero condition - Steady State)

Vas needs 30uA to pull the 6ma (Gain = 200). Also it will create .625V on its base.

Thus the Vas Driver needs to output 30uA + .625V/1kohm = 30uA+625uA = 655uA.

The Vas driver needs 3.275uA to pull the 655uA (Gain 200). Thus the current mirror must also pull 3.275uA which will cause it to output 655uA. 20uA of this will be used for the base currents (2*10uA) and the rest must be shunted, so 635uA needs to go away.

Using the 47ohm Resistors I get 94mV across the resistors + .625V for the transistor and I come up with 1132ohms. Yay, a respectable number!

So now to make a simple equation for perfect symmetry under no signal conditions using a current mirror with a buffer, and an EF VAS stage.

Current Source Pulldown Resistor =
(I_Tail / 2 * R_CMirr + .625)/[(.625/R_PullD + I_Vas/Bv)/Bv*Bc-I_Tail/Bc]

Where:
I_Tail is the tail current
R_Cmirr is the current mirror emitter resistor
r_PullD is the VAS driver pulldown resistor
I_Vas is the CCS value from the VAS stage
Bv is beta of the VAS transistors
Bc is beta of the Current mirror

This can be highly simplified for normal values of the pulldown resistor. Assuming it is significantly small and the Betas are significantly high.

0.8*R_PullD*Bv/Bc*(I_Tail*R_CMirr+1.25)

which evaluates to 1150ohms which is as close to 1130 as you will get for normal resistance values. Looking at this, as R_CMirr goes up, so does the correct current mirror pulldown.

This is all of course assuming that the correct thing to do is to match the currents at zero signal... Which I think is still being argued. However, the voltage matching at the top of the transistors is obscured by the ability to read a difference, more likely to come from the emitter resistors being slightly different.

When Cdom comes into play at higher frequencies the whole analysis goes out the window because you will be pulling the current to control the drivers through the low impedance Cdom. I think this is where high frequency distortion comes from, the only way to stop it is to have a powerful input stage or have it buffered from Cdom somehow. This distortion is where I believe that the emitter Current mirror resistors will need to be small in order to be able to shunt this driver current. Possibly, this makes an argument against the EF stage and to the Buffered VAS stage.

Next Idea? We'll see later.
Attached Images
File Type: jpg Current Mirror Fixes.jpg (62.5 KB, 86 views)

Last edited by buzz1167; 6th September 2010 at 08:01 PM.
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Old 7th September 2010, 09:16 AM   #15
AndrewT is online now AndrewT  Scotland
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I would need to check again, but first read through, indicates you understand where the currents are going and why they are certain values.
Once you can estimate the currents, you can move on to voltages and resistances.

Now you are ready to use a simulator to do all the arithmetic and you use your brain to ask the right questions.

Look up cascoded VAS and see why the cascode can offer advantages that suit the current demands from the LTP stage.
BUT,
the cascode has a high output impedance. This demands an EF or a three stage output using pre-drivers, or maybe both!
Going back a post to Self's 6 VAS options.
I think D+E is superior to C and all the others. F may be a close second.
Look around this Forum for good VAS stages that involve extra transistors as implemented by our experts.
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Last edited by AndrewT; 7th September 2010 at 09:21 AM.
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Old 7th September 2010, 09:44 AM   #16
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Quote:
Originally Posted by AndrewT View Post
mirror 3 is set up wrongly, if you ignore the extra resistor and transistor in the mirror.
The I1=0.4mA must equal the IbVAS + Ir2, since the same transistor is used for the EF and for the mirror.
Ir2~0.6V/330ohms
Thanks AndrewT.
So if I correct Mirror3 maybe performance can match the Mirr1 and Mirr2.
Now I find your suggestion a bit unclear. It is probably my english.
Tell me what resistors to change and new values.
I will then ask my sim what it thinks abou it.

To optimise I tried several different alterations.
The diagram shows the lowest THD I could get.
----

When speaking of mirrors I think we must distingues between things:
1. DC-precision
2. AC-precision and distortion.
The best performance THD need not have the absolut uA precision.
There are other circuits than audio amplifiers
where we measure things. Here we should go for max current precision.
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Last edited by lineup; 7th September 2010 at 09:49 AM.
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Old 7th September 2010, 09:59 AM   #17
AndrewT is online now AndrewT  Scotland
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post14 seems to have got it.
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Old 7th September 2010, 10:05 AM   #18
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I was looking at the type E VAS and I think will try that next mainly because of the comment I had made before about separating the input pair from the drivers. When Cdom comes into play the input pair might have to directly control the drivers in an EF setup, but with a buffer I think it should be more linear and have more gain in the high frequency ranges.

I am going to build the amp with a type E VAS as it stands and maybe then if I am happy I will prototype a final board.


Protection Circuit
I am already on to more drawings. I have created a layout of a "Anti Thump" and a DC Offset Detector using a 555 timer and a dual op amp package. Might anyone have some suggestions to my madness? I have stolen ideas from circuits I have seen, but I'm ok with that.

The Idea is to turn on the relay with the 555 timer by making the output go LOW. Under startup conditions, the trigger will be low because it will still be charging its capacitor thus the circuit will start off correctly and the output will be HIGH. The output will stay stable until the 7Sec Threshold Cap charges, then it will go LOW and remain there until the circuit is restarted by pulling the trigger low again.

I use the op amps to intentionally pull the trigger low by use of an NPN transistor connected to their output. If either of the Op amps turn on (go High) then the NPN will discharge the caps and the circuit will turn off the Relay. If the Fault was hit by accident, then the circuit will just wait 7 seconds and re-engage. However as long as the op amps show DC voltage above 1.5V the circuit will stay off. The input Cap and Resistor were chosen for a low frequency filter and to separate the capacitor from the output. 80k might not be enough but I started there...

What do you think?
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File Type: png ThumpAndVoffset.png (35.8 KB, 70 views)

Last edited by buzz1167; 7th September 2010 at 10:15 AM.
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Old 7th September 2010, 11:40 AM   #19
AndrewT is online now AndrewT  Scotland
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hi,
I can't read the diagram clearly.
Are the two opamps set up as a window comparator?
If so, then this is an excellent way to detect and trigger for excessive output offset.

Zener protection across the opamp inputs would allow more sensitivity of the DC detection with a much lower input attenuator. You may be able to omit the 10k completely. The 0.8s filter will then be loaded with a much higher impedance load than the present 50k. This seriously compromises the existing 82k filter's response.

This then lets you change the component values of the filter from 82k/10uF to ~470k/1uF with virtually no leakage current through the non existent electrolytic.
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Last edited by AndrewT; 7th September 2010 at 11:47 AM.
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Old 7th September 2010, 11:50 AM   #20
AndrewT is online now AndrewT  Scotland
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Self's pics E & F are both good.
Self rejected them on commercial and absolute THD grounds.
I think they both show potential sound improvements over the EF fed VAS with massive Cdom.
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