Combined Topology - Thoughts?

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I hope I have drawn a window comparator, I was trying to t least :D .

When you say "Zener protection" I assume you mean some circuit like I have shown below? I found it called a "zener limiter"... I would assume that I could use 9V Zener diodes and accomplish the same function as I wanted before with the voltage divider and be useful for almost any voltage output.

I will now be able to detect ~.3V offset after around 1 to 2 seconds which I believe is just fine. Thanks for that info I didn't really think about how much I was "loading" the filter but the op amps should not load it significantly.

I think they both show potential sound improvements over the EF fed VAS with massive Cdom.

What is massive to you? Is 100pf considered a lot? I was hoping that on my last iteration I could drop to 68pf. Will I need to look at different values based on a Buffered vs. EF VAS?
 

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New Amp!

I have implemented the Buffered VAS stage as shown in Doug Self's Simple text. I chose type E over Type F only because I don't have any VAS PNP transistors... I will hopefully get to build this, this weekend.

I hope you like the design, and I hope it will sound decent!
 

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I will hopefully get to build this, this weekend.

I hope you like the design, and I hope it will sound decent!

I am sure it will be a good amplifier.
You have done a good job in research.
I think it will work.

68p Cdom cap.
This can be a good value.
But when amp is built, optimal value can be anything from 22p - 100p
If you have oscilloscope, you can use it.
Otherwise pick a cap value that keep stability.
Should be a bit more than the lowest value, that keep amplifier stable.
 
post22.
6mA for the drivers???
4mA for the LTP tail & the VAS? 50V & 4mA is 200mW for a To126 device.
Cdom <=39pF is OK, Cdom <=15pF would be a brilliant result if you can find the other compensation components/values to give adequate stability. I don't think 60degrees of phase margin is sufficient.
 
Hi,
what are the time delays in triggering the DC detect and cut off for different DC offsets?
Try +-Supply rail, +-20Vdc +-10Vdc +-2Vdc as well as your +-0.3Vdc
Try full output voltage at 20Hz & 15Hz & 10Hz & 7Hz & 5Hz. Which triggers the protection?

What effect does adopting lower voltage Zeners have on these triggering times / frequencies?
 
Firstly I'd like to talk about the cutoff frequencies for the amp. I should have looked at them and I'm glad that Andrew brought it up and reminded me. So here we go.

First of all I need to make an assumption, that the op amp doesn't take any input current. Now since the 470k resistor gives only 2ua at a 1V delta, this might not be a good assumption. However op amps can be chosen with care, such as the tl032 series which only requires a couple pA of input bias current. Thus I can make this assumption.

Now, lets get to it! First we can try it without the zeners. How do we get the voltage on the op amp from the voltage input to the low pass filter? Well you can use some electronic rules. Thus summing the currents at the capacitor gives us
(V_out-V_comp)/R = C*Dv/Dt

Where V_Comp is the voltage across the capacitor and comparators.

Assuming V_out = ASin(w*t) we can solve some long winded DiffEq and get.

V_Comp = A/((wRC)^2+1)*(wRC*Cos(wt) +Sin (wt))

Plugging in all the values to find when the V_Comp will set off the comparators (>.3V) we can create a small table...

Using new values of 470k and 10uF

12V Pk-Pk
2hz -> .20V No Turn off
5hz -> .08
10hz -> .04

30V Pk-Pk
2hz -> .50V Will Turn off!
5hz -> .20 No Turn off
10hz -> .10

60V Pk-Pk
2hz -> 1.05V Will Turn Off
5hz -> .41 Will Turn Off
10hz ->.20 No Turn Off
20hz -> .10

With this we can see that as the voltage increases, we loose low end capability. How do you fix this? Add Zeners!

If You use 10V-12V zeners to limit the input to the filter you get a different response, almost independent of voltage so long as the max voltage is higher than the zener voltages.

Running with 10V zener Diodes we can calculate below for a few values of the RC circuit.

470k 10uF
2Hz .51V
3Hz .35V
4hz .26V
5Hz .21V

470k 5uf
2Hz 1V
3Hz .69V
4hz .51V
5Hz .417V
6Hz .348V
7Hz .299V

470k 1uf
2Hz 4.1V
10hz 1.01V
20hz .518V

With any rail voltage significantly above 10V at max power using 10V zeners the above solution works pretty good. But only for small voltages on the comparator setting. When you increase the voltage marks on the comparator, these values could change significantly.

One more number of interest is how long it takes to turn off from a pure fault. I.E. transistor blows and speaker output goes to full rail DC.

For this you can derive another simple equation...

V_Limit = V_Zener*(1-e^(-t/(RC)))

Where V_Limit is the comparator Limit voltage (.3V in my case) and V_Zener is the voltage of the Zener diode. This equation assumes that your Rail voltage is above the Zener diode voltage, obviously this should be the case...

Solved a different way for Shutoff Time.

ShutoffTime = -R*C*Ln((V_Zener-V_Limit)/V_Zener)

For reference my Rail shutoff time is around .15sec. Using a 10V zener and an RC constant of about 5. RC=470,000*.00001 (10uF or 1e-5 or 10e-6 or "4 balls 1") Ok so enough fun. Heres a chart of RC constant Vs Zener Diode Voltage using a limit voltage of .3V.

Rail Fault Turnoff Time Using .3V Limit Voltage

Zener Voltage


3 7 10 RC Constant 1 0.11 0.04 0.03
5 0.53 0.22 0.15
10 1.05 0.44 0.30
20 2.11 0.88 0.61
 
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Sorry, the Table got messed up when I pasted it so, here's a better version below.

I also updated the schematic based on my findings for the op amp. I increased the transistor pulldown resistor as to not load the comparator so much and I increased the RC filter Cap to 10u.


Heres a chart of RC constant Vs Zener Diode Voltage using a limit voltage of .3V.

Rail Fault Turnoff Time Using .3V Limit Voltage
Zener Voltage along the top and RC down the Side.

3V 7V 10V
1 0.11 0.04 0.03
5 0.53 0.22 0.15
10 1.05 0.44 0.30
20 2.11 0.88 0.61

For reference, I will use an RC of 4.7 and Zeners of 10V.

You will see that the lower zener voltages causes the circuit to take longer to respond. Thus the same effect occurs with the cutoff frequencies, lower zener voltages will allow you to go to lower frequencies. Likewise, higher V_Limit's will have similar effects, although harder to calculate the frequency response by hand... We also never want V_Limit to approach V_Zener. As V_Limit gets closer to V_Zener the times will get VERY long and when V_Limit is above V_Zener, the configuration no longer operates, so don't do that :)
 

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6mA for the drivers???
4mA for the LTP tail & the VAS? 50V & 4mA is 200mW for a To126 device.

Are you suggesting that those are large values or small? They are 1.2W free air devices are they not? It seems to say that they could run up to 7W with a heatsink...

Heres the reasoning, other than taking values from people...

The 4ma on the Input stage insures that we can have two things. Large emitter degeneration on the input and nfb transistors, which attempts to create linearity in the transconductance stage. I might even increase those 100ohm degenerators some more if I do a bit more research.

It also ensures that when the Cdom decides to create a low impedance across the VAS that the input stage has enough power to drive the high frequency data through to the buffer without so much VAS gain.

The 6ma for the VAS buffer was chosen based on nothing, other than just driver requirements multiplied by an arbitrarily large factor. Its possible I don't even need this stage, as is shown with the simpler EF setup.

The 6ma bias for the drivers is based on pure capacitance and frequency concerns for turnoff time... I don't think its out of the question since the drivers had 6ma draw on them before with a 200ohm resistor, why argue against use of a current source instead?
 
I am particularly aware of the driver current limit.
6mA CCS feeding the diamond limits the base current to the output device.

What hFE would be needed to drive 20Apk into a speaker load with Ib=6mA?

Now look at the Ic vs hFE graphs that the output device manufacturers publish.

A normal two stage EF works differently.
I have not used a diamond in the output so I'm guessing at it's high current operation.
Find corroboration that your proposal will work. That's what I said way back.

I also see a coincidence in selecting the two CCSs at the same 4mA current to feed the LTP and the VAS. This seems somewhat random. I cannot say it is wrong. It will work as you propose but are you selecting optimum operational currents to obtain good performance from your selected devices in their particular duties?
 
I'm not sure why you are thinking that the max current that can be driven with the drivers is 6ma... I hope I have not drawn it wrong...
I have tried to setp the circuit such that the ccs's are driving a biasing current, the drivers can and should output more than 6ma, up to whatever is required and the difference in current will be what is output to the base of the output transistors. I think this could be lowered but I also expect to add another output device.

How would I go about finding the optimum current for the vas and input stage?

Selfs article that I read seems to make it seem like bigger is better for the transconductance stage (input stage) mostly because it allows linearization by degeneration. Does this not hold true?
 
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Success! Or at least it works...

I figured I'd post some pictures of my final setup. I ran the amp topology that I previously posted, with some slight modifications. Changed the Input Degeneration resistors from 100 to 200ohms. Changed the current mirror resistors from 47 to 22 ohms. Used a 20k by 600ohm-220uF NFB.

As far as performance goes, it looks like the ccs's deal better with the high frequency stuff than the simple resistor/cap setup. When I had the old setup, I could subtract the signals and get an error with a little spike in it and it wouldn't go away (out of sight) unless I over biased it a bit and then the transistors would try to runaway. No fun... This one can be "underbiased" for lack of better terms and not show that spike. I've tried to induce runaway by running it full power which is currently 100W RMS into 4 for 10 or 20 minutes but I will test again with the full rail at 200W into 8. This 100W test did cause the static current to rise from 15ma to 40ma but it dropped back in a reasonable time, and since this was not even actively cooled I figure I'll be ok.

I will build the dc offset detector sometime. Maybe next weekend, testing it might prove interesting... I'm gonna need to rig up some resistors.

For sure I am going to get some production boards made based on this design but I'll need to learn to use somebody's software to make the trace drawing. So we'll see how that goes. I'll need 4 of them, but i've been looking at prices and I'll probably end up buying a few more and selling them on ebay or here if anyone's interested?

Below I have pictures of the entire setup, then a closeup of the top and messy bottom. The random wires are for jumping power to the transistors and current sources in the middle, as well as all the separate grounds I have. I don't know what I'm going to do with them all on the prod board yet, I'll have to look into it. I plan to fix all the jumper wires by simply using a 2 sided board.
 

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