How to bias mosfet in Class-A

[Anchan]

Hello,
I have a question about correctly biasing a mosfet for class-a operation. I am a relative newbie, so sorry if I am not interpreting the data sheet correctly. Thats why I need you guys.

Specifically, I am using Nelson Pass' "balanced zen line stage" as my input stage.
http://passdiy.com/pdf/balzenpre.pdf
I'll be using the IRF510 FET:
http://www.vishay.com/docs/91015/91015.pdf

This stage must take the signal from my DAC, which has a rather hot 2.75Vpp single ended, 5.5Vpp balanced signal. At the output of the zen stage, I need about 20Vpp. So this is only roughly 4X gain.

In Nelson's article, he has the source of Q1 and Q2 set to around -3.5 to -4V.
In looking at the Vgs vs Id graphs on the data sheet, this makes sense if the input signal is in the 1Vpp range. But in my case, where the signal driving the gate is relatively large, what to do?

The graph in the data sheet has Id drawn in log scale, so I manually redrew it in a linear scale, so I can see the curve correctly (attached).

What I see is a large hump at 5V which is where I presume the FET goes from linear region to saturation? Because my input signal spans almost 3Vpp, this is larger than the whole linear region.

So my choices, in my mind, are to voltage divide the original signal down to around 1Vpp, and set the Source to around -4V. Or I could use the full 2.75Vpp input signal as is, and bias the source pin to -6.5V or so. Here I presume I would be running the FET in saturation mode, which according to the graph, still has a very nice 'linear' look to it.

Are these observations, assumptions correct? Am I interpreting the graph correctly? Could someone give me some informed advice?

Thannks

[ervinl]

Based on my experience, if Vgs is too high, it is true if it can go to saturation for certain MOSFET, but not for the other MOSFET (higher Id and VGs saturation). If this is for linestage, then the proper handling may be to reduce the Vgs bias. Usually around 2V is enough to be in linier mode (depends on MOSFET). If you need higher Vgs saturation, may be you can try higher MOSFET like IRFP 240. But this is normally for power amp, not linestage. Or use lateral, with lower Vgs.

Ervin L

[abraxalito]

Originally Posted by Anchan

The graph in the data sheet has Id drawn in log scale, so I manually redrew it in a linear scale, so I can see the curve correctly (attached).

What I see is a large hump at 5V which is where I presume the FET goes from linear region to saturation?

Your re-drawing of the curve has distorted it, so the 'hump' you're seeing is an artifact of that. The ten lines below the 1A level need to be compressed down to one line as that range is from 0.1A to 1A. As it is now, the lower half of your graph has 0.1A steps and the upper half, 1A steps.

[Anchan]

Originally Posted by abraxalito

Your re-drawing of the curve has distorted it, so the 'hump' you're seeing is an artifact of that. The ten lines below the 1A level need to be compressed down to one line as that range is from 0.1A to 1A. As it is now, the lower half of your graph has 0.1A steps and the upper half, 1A steps.

Ahh, yes you are right about that. Thanks for catching my mistake. It is difficult to see the linearity of the gain when they use the log scale. Any tricks to eyeballing this as I browse for appropriate FET's?

[abraxalito]

Originally Posted by Anchan

Any tricks to eyeballing this as I browse for appropriate FET's?

I can't see any reason not to feed the full 5.5p-p signal into this circuit. The -4V bias is only the quiescent (no signal) condition and its determined by how much current you want through the FET in this state (set by the 2 750R resistors). As you apply more voltage, the source voltage will follow the input as its effectively a source follower, so it will range from -1.25V to -6.75V. If your supply rails can handle this (seems they'll be high, around 80V?) then no problem as the signal is only a small fraction of the DC bias.

[CBS240]

Originally Posted by Anchan

In Nelson's article, he has the source of Q1 and Q2 set to around -3.5 to -4V.
In looking at the Vgs vs Id graphs on the data sheet, this makes sense if the input signal is in the 1Vpp range. But in my case, where the signal driving the gate is relatively large, what to do?


Thannks

Hi

I think you may be mis-understanding the relationship of Vgs and Id relative to the circuit. The source voltage is not fixed. It appears in fig 3, Id bias is 28.2V/750R or 38mA. For a 20Vp output signal, the change in Id is +/- 20V/750R or ~27mA. So the AC load line plots (Id vs Vds) between 11mA and 65mA, with Vds of 14V (@65mA) to 54V (@11mA). A current swing of 54mA is not going to require a very large change in Vgs. The source voltage will follow the signal voltage on the gate, less this small change in Vgs. Vgs threshold is not very relevant, one can simply adjust a resistor value to make the difference for any fet of suitable SOA. IRF610 is a typical hex type switching fet. They are all similar.

As a side note, I find it easier to understand FETs by the variables relationship to transconductance (Gm) as opposed to current flow as they are voltage controled devices. BJTs are current controled and so it is easier to anylize the circuit using current flow.

[abraxalito]

Originally Posted by CBS240

BJTs are current controled...

A very popular myth but in reality (physics) they're exponentially voltage controlled. MOSFETs are square-law voltage controlled.

[CBS240]

true, but in anylizing a circuit, I find it is easier to think of them as such.

[abraxalito]

Originally Posted by CBS240

true, but in anylizing a circuit, I find it is easier to think of them as such.

I tend to analyse them assuming they've got 0.6-0.7V between the base and emitter, then use gm (as you suggest) to find out what the currents might be. hFE is one of the parameters which is not very tightly controlled in bipolar transistors, usually it has quite a broad spread and, especially for power devices, its highly dependent on Ic. gm in bipolars is much easier to 'get' as its only a function of the collector current, not the geometry as is the case in MOSFETs.

[Anchan]

Originally Posted by CBS240

Hi

I think you may be mis-understanding the relationship of Vgs and Id relative to the circuit. The source voltage is not fixed. It appears in fig 3, Id bias is 28.2V/750R or 38mA. For a 20Vp output signal, the change in Id is +/- 20V/750R or ~27mA. So the AC load line plots (Id vs Vds) between 11mA and 65mA, with Vds of 14V (@65mA) to 54V (@11mA). A current swing of 54mA is not going to require a very large change in Vgs. The source voltage will follow the signal voltage on the gate, less this small change in Vgs. Vgs threshold is not very relevant, one can simply adjust a resistor value to make the difference for any fet of suitable SOA. IRF610 is a typical hex type switching fet. They are all similar.

As a side note, I find it easier to understand FETs by the variables relationship to transconductance (Gm) as opposed to current flow as they are voltage controled devices. BJTs are current controled and so it is easier to anylize the circuit using current flow.

I think you are right. I am misunderstanding the relationship of Vgs and Id relative to the circuit. And you are right- it makes perfect sense that the source is not fixed, now that you mention it. I need to hit the books to follow the rest of your statement though. I have the Art of Electronics, and I'll have to dig online a little further. In the past, my only experience w/ mosfets was to use them as switches, not as gain devices, so this is a bit new.