Hi OS,
This is great data. When you talk about differences in Vbe that develop with temperature in these experiments, I assume you are talking about relative changes among the devices with respect to where each one's Vbe started (in other words, you did not start with all of the devices with measured Vbe within, say 1mV of each other.
My impression from you post is that even when the devices are crowded together, the inner hotter transistors only show a decreased Vbe of perhaps 3-4 mV. This seems quite small and insignificant in the overall scheme of things, especially given that the 5 pairs of output transistors would likely not match that well in the first place. A 4mV difference would imply only about 2C, which almost sounds too good to be true.
Am I missing something here?
Cheers,
Bob
Hi Dave,
One of the incentives of using a helper transistor with a current mirror is that, just as Bob pointed out, it helps keeping the mirror transistors away from quasi saturation. Simulations I did indicates that, in addition to increased mirror degeneration resistor value, it would be a lot better to use a helper diode if a helper transistor is not to be used than to simply short out the B-C on the reference side of the mirror. The diode increases the Vce of the mirror transistors by a forward drop (0.4v-0.5v at a few uA), and that makes a substantial difference in THD-20 by as much as 26dB.
I could have thought of using resistors in place of the LTP cascoding transistors. It certainly should work. Thanks for bringing it up. There could be a down side of it, these resistors would probably have to be one size larger for the power dissipation, and if that is the case, two of them would take more PCB space than one dual transistor package. I'll hit LTspice and see how it goes.
Can you then show some small schematics with values and measurements so we Can see what is going on?
No , you are not missing anything.
Here is a representation of what I think is a problem.
1. - Vbe is close to the first/second pair (5 pairs close together) -
- 15 - 14.5 - 15.2 - 15.7 - 14.3 - @ 20C after turn on.
- 14 - 15.3 - 16.5 - 14.8 - 14 - An example with ON semi NJW's @ 50C.
Sanken MT-100's would get > 18mv , center pair.
As you see , the average is the same between the 5 pairs.
BTW , Extrusion was @ 2C cooler at the outer pairs.
2. -Double spaced TO-3p's @ 22mV (100ma) biased (3 pairs) would be
- 21.5 - 22 5 - 21.8 - less than one C drop at the outer devices.
This effect still holds true if the Vbe was out on wires and
monitoring the center pair .
3. -The bigger MT-200 3 pair is spread nearly equally out across 200mm
(on a 300mm extrusion). It is -
- 22.1 - 22.3 - 21.7 - ... this changes maybe <.2mv right up to 60C !
I looked to the 5-8 pair Pass Labs/ Parasound amps ,. They did
what my new PCB does - give each pair "equal acreage" on
the extrusion.
The Vbe in each case is just monitoring T at one set physical point
on the extrusion . Individual devices will assume unique Vbe's ....
contributing to the "average".
Examples 2 and 3 are quite acceptable to me. I just received my 304mm
extrusions and will see what I can do about example # 1.
I'm surprised you said 4mV WAS acceptable - I'm just a "perfectionist".
OS
This depends on quasi-saturation behavior. If you try to use >50V BJTs (2N5551, KSA992...) in the current mirror then you can plainly see in the datasheets that it is operating in the quasi-saturation region which causes a resistive collector. The BC5xxC and BC3x7-40 have almost no quasi-saturation to speak of however, and these will perform very well in a 0Vcb current mirror as long as the voltage does not drop far below 0Vcb.
This does depend on the VAS somewhat. If your VAS has a lot of degeneration then you can actually increase distortion by increasing the AC voltage at the current mirror collector. But unless your current mirror is operating in quasi-saturation, raising the collector voltage won't necessarily result in a large benefit.
If your current mirror is heavily degenerated, the degeneration voltage can also cut into Vcb. So if your CM is degenerated at 300mV, and your VAS input is 680mV, your mirror collector will have -380mVcb.
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Two quick notes.
With helpered current mirrors, one has the choice of how much current should flow in the helper transistor. Sometimes no pull-down resistor from helper emitter to negative rail is used, while at other times such a resistor may be used. This choice will affect the value of the added Vbe drop. I often do not trust the non-use of some amount of pull-down current. In some cases, one might go as high as 10% of the current in the mirror. For example, if the output node of the current mirror is likely to have a voltage swing with a high slew rate, the pull down current should be at least as much as the maximum slewing current through the base-collector capacitance. This of course is not the case when the output of the current mirror is driving a VAS. The pull-down current also might be selected to cause the Vbe drop of the helper to be close to that of some other transistor in the circuit - perhaps the same as the emitter follower in a 2T VAS. The amount of the pull-down current may also affect the ft of the helper, possibly having some effect on any stability issues.
Secondly, an IPS cascode may be necessary in regard to voltage rating of the input transistors compared to the rail voltages. Often, transistors that are optimum for IPS may not have high voltage ratings. This often goes for JFETs, dual monolithic BJTs and high-beta BJTs. So the voltage issue might trump the dissipation issue anyway. I don't recommend adding series resistors in the collectors to drop some of the voltage unless they are bypassed in some way to avoid possible Miller effect interactions. Adding 2 transistors to make a cascode is pretty cheap, especially if an appropriate cascoding base voltage like 12 or 15V is already available. Perhaps out of superstition, I usually put 100 ohms in the emitter of each of the cascode transistors.
Cheers,
Bob
Just a few pictures ....
I have my metal !!
First picture (below 1) , is the 3 pair vertical amp. You see the close
Re readings (<1mV). P and N have about half the extrusions "acreage" ,
but the top of the sink is 2C hotter (convection).
(below 2) is the horizontal .4C/W and (what I know) will give me nearly
uniform temp from end to end.
The "trick" seems to whether each pair has a equal # of complete fins.
5 close together pairs , the middle pair would only have a
couple fins versus 10 or more for the outer pairs (on the horizontal extrusion).
Second photo , each pair has 6 complete 150mm fins (2C /W each).
On the first photo , each gender has 7 fins (vertical .8C/W).
Convection (vertically) affects the NPN's or PNP's mV across Re (as shown).
So , your final orientation (and extrusion type) is yet another factor
to consider.
OS
I have my metal !!
First picture (below 1) , is the 3 pair vertical amp. You see the close
Re readings (<1mV). P and N have about half the extrusions "acreage" ,
but the top of the sink is 2C hotter (convection).
(below 2) is the horizontal .4C/W and (what I know) will give me nearly
uniform temp from end to end.
The "trick" seems to whether each pair has a equal # of complete fins.
5 close together pairs , the middle pair would only have a
couple fins versus 10 or more for the outer pairs (on the horizontal extrusion).
Second photo , each pair has 6 complete 150mm fins (2C /W each).
On the first photo , each gender has 7 fins (vertical .8C/W).
Convection (vertically) affects the NPN's or PNP's mV across Re (as shown).
So , your final orientation (and extrusion type) is yet another factor
to consider.
OS
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Thanks a lot, Bob. That was reassuring.
I started out with a Darlington 2T VAS with the amp project and later changed to the Hawksford cascode VAS as seen here #5659 This VAS has a much heavier degeneration than what you seem to usually recommend. Because of the heavy degeneration a helpered current mirror can work with it. This circuit also simulated as good a THD-20 at full power as a 2T EF enhanced VAS would. What would be the significant down side, if any, to such a heavy degeneration? I'll post a full circuit .asc that I simulated on when I get home.
I've just seen your post of Two quick notes about the helper pull-downs and the IPS cascoding. All good points. much appreciated. I'm running a pull-down current through the helper transistor much larger than what would be in case of a 2T VAS following the IPS. Because I have a 1T VAS and I wanted the helper transistor to draw about the same amount of base current from the mirror as does the VAS draw its base current from the flip side of the mirror. So the helper is rich running at about 6mA. I did some loop gain plots of the same amp circuit, one with a transistor helpered mirror, the other with diode helpered mirror, every thing else being equal the plots are virtually the same but some very subtle difference far out beyond 30MHz.
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Hi
I must apologize as I apparently made a mistake that I still don't realize what exactly it was that got me the 26dB difference in THD-20 between the two circuits. I have been unable to repeat it.
I'm posting three pictures of the THD-20 simulation showing the various base current arrangement to the current mirror load has to the simulation results. A diode-helped current mirror has about 11dB THD-20 advantage over a mirror that has direct short B-C on its reference side. 11dB, not 26. Sorry, my bad.
A zip file containing these circuit is attached, as well as the transistor models used in these schematics.
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I have my metal !!
......
So , your final orientation (and extrusion type) is yet another factor
to consider.
OS
Sexy, whatever orientation
How would you attach the IPS boards in a chassis then, in a right angle with the OPS boards or using wires?
If the current mirror is heavily degenerated, the cutting into the Vcb will not be a problem as long as you are using a 2T VAS, since the VAS input DC level will be about 1.3V from the rail plus whatever voltage there is across the VAS degeneration resistor.
A heavily degenerated CM reduces the noise contribution of the CM, which is a good thing.
All else remaining equal, I like to degenerate the VAS to the same degree as the CM, so the voltage drops of the CM Re and VAS Re are the same. Under these conditions, degeneration of the CM does not cut into Vcb.
Degenerating the VAS does not generally increase the voltage swing at the output of the CM very much, since the VAS transistor current swing is fairly small under most normal conditions. Note also that the shunt feedback provided by the Miller compensation capacitor tends to keep the signal swing at that node small.
Cheers,
Bob
Sexy, whatever orientation
How would you attach the IPS boards in a chassis then, in a right angle with the OPS boards or using wires?
I've had "critics" denigrate the modular approach. The high Z 3EF inputs
are just 35mm away from the IPS (at a right angle).
I use long copper "pins" 35mm long. Slide them into the euro's , listen to
a new input stage. All are a standard 5.2 - 5.5ma , so the OPS's bias
has little change.
I know it might be a little "anal" , but I've also made most input stages
with ultra stable Tc. Most change <.2ma from 0-50C (5.2- 5.5ma Ivas).
With 10 input stages , one must have a "standard".
OS
If the stage was outside of a feedback loop that would be true. Miller compensation universally reduces gain and so the VAS input must be larger to reach the demanded output. I do agree with the rest though. It's just I wanted to show a situation that would get people to think about the where exactly the limits are rather than just saying "do it this way and you'll be fine". After all there are many different VAS designs, if we discuss this topic only on the ones we like, we miss the big picture of being able to know the limits of any given design.
Is there a thermal resistance curve posted anywhere for foamed aluminum heatinks?
Hi
I must apologize as I apparently made a mistake that I still don't realize what exactly it was that got me the 26dB difference in THD-20 between the two circuits. I have been unable to repeat it.
I'm posting three pictures of the THD-20 simulation showing the various base current arrangement to the current mirror load has to the simulation results. A diode-helped current mirror has about 11dB THD-20 advantage over a mirror that has direct short B-C on its reference side. 11dB, not 26. Sorry, my bad.
A zip file containing these circuit is attached, as well as the transistor models used in these schematics.
Your circuits are pretty much 2 symmetrical opposing "blame-less's".
I tried the helper diode/no helper diode in simulation (below 1 and 2).
Besides the fact that the diode brings both sides of the CM to Bob's
optimum (1.3V CM + .3V VAS Re) , the plots look (almost) the same.
A more careful exploration show H4 and H5 drop a couple of db. I did
not have any large (10db) increases with or without the diode.
Just a 1-2ppm THD20k drop with the diode.
I'm not sure if you could hear those couple db H4/5 .... but the diode
does even the CM out (voltage wise).
Some call the diode " magic" , my present blameless simulation is the
first one good enough to actually see those couple PPM.
10c diode - why not ??
OS
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So current sources in a diamond just aren’t that important then? (ref: post #5677 & #5698)
So with a buffered VAS (2T VAS) presumably two diodes in series, or a diode + helper transistor, in the CM would be a good idea?
Bob, do you have any comments on the VAS/TIS OS posted in #5662? Have you ever tried anything like this?
I'm not sure if you could hear those couple db H4/5 .... but the diode
does even the CM out (voltage wise).
Some call the diode " magic" , my present blameless simulation is the
first one good enough to actually see those couple PPM.
10c diode - why not ??
OS
So with a buffered VAS (2T VAS) presumably two diodes in series, or a diode + helper transistor, in the CM would be a good idea?
Bob, do you have any comments on the VAS/TIS OS posted in #5662? Have you ever tried anything like this?
Hi Harry,
That VAS is a neat idea, folding the first EF transistor and using its emitter voltage to drive the cascode base through an offset, so as to effectively get the Hawksford cascode effect. With the first EF folded, the input dc voltage is essentially that of the main VAS transistor, so I guess that is why the degen resistor is so high at 100 ohms to give the preceding CM some headroom. Not sure what the standing current is set for.
Not sure about PSRR effects from the folded EF biasing resistor that straddles the rails, effectively. I suppose the resistor could be replaced by a floating current source that could handle 2X the rail voltage.
Cheers,
Bob
Thermal resistance and volume have a linear relationship (example graph in arrl handbooks)
Solid and foamed aluminum differ in specific surface area, thermal resistance of a foamed heatsink is equivalent to the one of a solid aluminum block with a volume which is higher by the ssa factor difference (m2/m3).
The ssa factor is provided by the foamed aluminum manufacturer.
(Thermal conductivity of foamed aluminum is lower than for solid, e.g. 100W/m.k for open cell foam with 50% porosity. But surface area per volume/mass can be gigantic. Plus even distributed heat transfer, one can even easily trim the outer side of a heatsink block to compensate for a non-infinite heatsink length)
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