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Old 14th November 2011, 11:17 AM   #2281
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Default Miller loop

Quote:
Originally Posted by Olivier73 View Post
...........
Hi Edmond,
Have a good beer. I am eager to learn more about assessing the loop properties. I didn't do any testing today so nor did I capacitively load the OPS. It is indeed better to analyse ad fundum the VAS properties instead of shooting at it with capacitive loading and other taunteries to see if it survives.
..............
Cheers !
Hi Olivier,

First, let's start with the VAS. In order to accurately simulate the loop gain you have to look at the voltage gain as well as the current gain. How to do that with MC is describe here: Simulating Loop Gain - Spring 1997 and here: Loop Gain
However, this method is a bit cumbersome, as you need an additional copy of the circuit. To avoid this extra copy, you can look if there is a suitable point to break the loop where only one the components (either voltage or current) is very large with respect to the other component.
In this case there is such a point for the voltage component: between the emitter of Q19 (having a low impedance) and the base of Q23 (having a high impedance). Now we break the loop by inserting a huge inductor (L1), which blocks AC signals but preserves the DC operating point.
Via a large capacitor (C13) we inject a voltage into the base of Q23 and looks what happens at the emitter of Q19, which acts like an output.

Of course, we are not done yet, as there is one more VAS. So we inject the signal also into the base of Q26 via C14 and combine the output signal from Q20 to a common point (U) via C10. Needless to say that we also have to break the loop of the second VAS by means of L2 (fig. 1).

Now we simply look at the relationship between V(vin) and V(u) (fig. 2).
Knowing that this method is not accurate (and basically wrong), I've compared the results with Tian's method. Happily, the results were almost identical.

As the ULGF of your original circuit was pretty high, I've adjusted several components: The Miller and TMC caps are now 47pF resp. 220pF and lead lag compensation at the VAS inputs is 330pF in series with 15 Ohms.
Now the phase margin is 94 degrees at an ULGF of 11.5MHz, that is, simmed with above method as well with a Tian gain probe.

Regarding lead-lag compensation at the VAS output (as suggested by Walter) I prefer to put this additional compensation at the VAS input, as it does a better job of suppressing HF ingress (courtesy of Glen K.)

BTW, increasing the compensation caps has a price: more distortion! But what do you prefer: the lowest possible distortion or a more stable amp?
I would say, don't push this amp to the limits. Moreover, you don't know yet what will happen when you connect the final OPS to this front-end.

Cheers,
E.

PS1: I've also included a MC file (*.cir.txt)
PS2: The (small) phase dip at 400kHz is due to TMC)
Attached Images
File Type: png RS9-Miller-SCH.png (12.9 KB, 277 views)
File Type: png RS9-Miller.png (15.7 KB, 277 views)
Attached Files
File Type: txt RS9-Miller-v.CIR.TXT (79.7 KB, 9 views)
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Old 14th November 2011, 11:48 AM   #2282
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Default Common mode contol loop

Quote:
Originally Posted by Olivier73 View Post
.................
No I did not determine UGFL for the CMCL (I am simply not capable of doing
.............
Thanks in advance !

Olivier
Hi Olivier,

Next, how to determine the gain and phase of the CMCL.
Again, better use a Tian gain probe, but also in this case we can keep it simple: break the loop by means of huge inductors and look at the voltage components.
Opposed to the Miller loop, now we have to inject a differential test signal at the base of Q15 respectively Q16, and look at the differential output voltage at node A and B (i.e. V(A,B)). Simple, isn't it?

Notice that the ULGF (255kHz) of this circuit is lower than in my previous sim. This is because the lead-lag compensation at the VAS inputs, which has been changed, has a marked influence on the behaviour of the CMCL. Also notice that I've increased R29 & R30 from 100 to 150 Ohms for a slightly better phase margin.

For more details, just download (and run) the MC file.

Cheers,
E.
Attached Images
File Type: png RS9-CMCL-SCH.png (9.0 KB, 266 views)
File Type: png RS9-CMCL.png (15.1 KB, 241 views)
Attached Files
File Type: txt RS9-cmcl-v.CIR.TXT (74.5 KB, 10 views)
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Last edited by Edmond Stuart; 14th November 2011 at 11:51 AM.
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Old 14th November 2011, 12:14 PM   #2283
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Default MC10

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Originally Posted by PHEONIX View Post
Hello Edmond

Apart from being able to do the Tian probe thing with MC10 is the package an improvement in terms of its convergence when compared to MC9.

Regards
Arthur
Hi Arthur,

I didn't notice much difference.

Cheers,
E
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Old 14th November 2011, 04:26 PM   #2284
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Default Moving target....

Hi Olivier,

Regarding post 2281 and the Miller caps, I've overlooked something: the emitter degen. resistors of the LTPs have been changed. I assumed they were still 47 Ohms and have, accordingly, adjust the Miller caps in order to keep the ULGF of the global NFB loop at a safe value. In the mean time, I discovered that they are now 120 Ohms. With these R's you can keep the Miller caps as shown in your posts 2258 and 2264, i.e. 33pF respectively 180pF. The TMC resistors however, I would increase them from 680 to 1000 Ohms.

Cheers,
E.
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Old 15th November 2011, 04:02 PM   #2285
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Hey Olivier,

What's the threshold voltage (Vgth) of you power FETs?

Cheers,
E.
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Old 15th November 2011, 05:14 PM   #2286
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Hi Edmond,
I had no time yet to check your explanation of loop assessing but I will soon !
My FETS are LATERAL type MOSFETS 2SJ162/2SK1058 and have Vgs of just under 0,7V. Never tested under high current conditions however. Reading in Bob's book this might become seriously higher when heavy current flows.
Cheers,
Olivier
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Old 19th November 2011, 05:08 PM   #2287
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Default MicroCap files and the heritage of Randy Slone (RIP)

In post 2281 & 2281 I've put MC10 files by accident. With MC9 you can't open them. Sorry for the inconvenience. MC9 files (a few) can be found here: HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles (a more appropriate thread for this topic).

Cheers,
E
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Old 19th November 2011, 05:36 PM   #2288
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Quote:
Originally Posted by Edmond Stuart View Post
In post 2281 & 2281 I've put MC10 files by accident. With MC9 you can't open them. Sorry for the inconvenience. MC9 files (a few) can be found here: HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles (a more appropriate thread for this topic).

Cheers,
E
Hi Edmond
In the thread you are linking to, you mention that you have tried different MOSFET models and none of them are "right". Why don't you use Bob's MOSFET models?
(Bob's models are of 2SJ162 and 2SK1056 not 2SK1058)

Cheers
Stein
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Old 19th November 2011, 07:02 PM   #2289
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Hi Stein,

I wasn't aware of the models from Bob. Where to get them, on his website?

Cheers,
E.
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Old 19th November 2011, 07:21 PM   #2290
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Quote:
Originally Posted by Edmond Stuart View Post
Hi Stein,

I wasn't aware of the models from Bob. Where to get them, on his website?

Cheers,
E.
Hi Edmond

Yes, In the Cordell models file. Cordell models.

Cheers
Stein
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