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Old 10th February 2011, 03:18 PM   #1481
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Originally Posted by Samuel Groner View Post
AC analysis is by definition carried out at infinitesimal AC level. To vary operating point add DC voltage sources in the feedback path (shifts output voltage) or DC current sources from the output to ground (shifts output current).

Samuel
Hi Samuel,

This is a good point. I think one can also just put a DC source on the input of the amplifier if it is DC coupled, at the same time loading the amplifier with a resistive or reactive load to obtain the desired combination of voltage and current.

This can also be done to a real amplifier; in fact in that case the operating point can be moved by a low-frequency sinusoidal input at, say, 20Hz. The higher-frequency small-signal test tone or square wave can then be added to the input signal. The low-frequency tone can be filtered out at the output with a suitable HPF so that one can then see the test tone at the output.

One could further backfeed the amplifier through a load resistor with a second LF tone at, say, 19Hz, to exercise many combinations of voltage and current. Such a test needs to be carried out with caution, however.

Cheers,
Bob
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Old 11th February 2011, 01:03 AM   #1482
davada is offline davada  Canada
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Default New TI regulators

Has anyone checked out these fairly new ultra low noise wide band voltage regulators from TI?

They look very promising.

TPS7A4901 and TPS7A3001

focus.ti.com/docs/prod/folders/print/tps7a4901

David.
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Old 11th February 2011, 01:22 AM   #1483
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http://focus.ti.com/lit/ds/symlink/tps7a4901.pdf

Yes, that does look more promising than their other recent offerings which include a high frequency charge pump on chip.
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Old 11th February 2011, 01:18 PM   #1484
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Probably best to move the last 2 posts to the super-regulator thread. fwiw, the Jung-Didden with AD797 is still quieter, but for a device in such a small package, this is really nice.
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Old 11th February 2011, 09:20 PM   #1485
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Originally Posted by godfrey View Post
Hi Bob
You gave a perfect example of this back here:

I was surprised by how bad the ringing was with TPC and decided to do a little investigation. My starting assumption was that reduced phase margin will increase the tendency to ring, but that you still have to kick a thing to make it ring. E.g. Rail sticking during clipping will give the circuit a nice kick when it "unsticks", and could initiate nasty ringing.

So my first step was to modify the VAS to get inherently clean, fast, symmetrical clipping. This resulted in a big improvement, but there was still visible ringing, and it was still much worse on the positive half.

That made me curious about whether the phase margin was varying with output level, so I tried a quick test with a staircase waveform. The first run showed the ringing getting slightly worse at higher levels, but about the same on both sides. Increasing the output level a bit revealed the problem, though.

When the NPN output device is conducting more than about 5.5A, the amp is totally unstable. Testing with various loads and output levels seemed to confirm that. Adding an extra pair of output devices fixed the problem (although it would probably still have problems above 10A, I didn't bother testing further.)

This was quite an eye-opener for me. I have thought it a good idea to operate output devices "below the knee" for other reasons (e.g. distortion), but it never occurred to me before that it might be important for stability too. It also served as a gentle reminder that checking bode plots under quiescent conditions doesn't even begin to tell the whole story.

Cheers - Godfrey
Hi Godfrey,

This is a really nice piece of investigative work, and the results are portrayed well. We should all bear in mind that these kinds of tests are very useful for real amplifiers - not just in simulation.

What power transistor models were you using?

Yes, ft droop can be a big problem with power transistors, even with many of the fast ring-emitter/perforated-emitter devices. For numerous reasons, it always seems wise to err on the side of more paralleled output devices.

However, it is always important to bear in mind that more paralleled devices means more capacitance to drive for the driver (and that that capacitance can increase dramatically when the output voltage is near the rails). Although it seems wasteful of power supply resources, it is also often wise to use Baker clamps or something similar to prevent the output transistor bases from ever getting closer than, say, 5V from the rails. Those extra couple of watts you get by letting the output transistors get really close to the rails can extract a penalty (not to mention increased vulnerability to ripple on the rail feeding through upon clipping).

Cheers,
Bob
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Old 12th February 2011, 01:29 AM   #1486
klewis is offline klewis  United States
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Default Spice models and simulations

Bob,

I'm enjoying your book; at least what I've read so far. I've also downloaded your spice simulations and want to thank you for sharing this work. My question is about the use and modification of the simulations. Using your simulations as a baseline, I've been changing the output configuration and re-running the simulations in comparison to the baseline. I would like to put my results up on this forum, with credit to you and disclaimers where I have changed the simulations. Is this ok with you?

Again thank you for all of your contributions and help this neophyte.

Regards,

Ken
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Old 12th February 2011, 01:40 PM   #1487
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Originally Posted by klewis View Post
Bob,

I'm enjoying your book; at least what I've read so far. I've also downloaded your spice simulations and want to thank you for sharing this work. My question is about the use and modification of the simulations. Using your simulations as a baseline, I've been changing the output configuration and re-running the simulations in comparison to the baseline. I would like to put my results up on this forum, with credit to you and disclaimers where I have changed the simulations. Is this ok with you?

Again thank you for all of your contributions and help this neophyte.
Regards,

Ken
Hi Ken,

Thanks for buying my book and I'm happy that you're enjoying it. I'm glad you've been able to use the simulations and models from my website, and I do plan to put up more models and simulations in the near future.

By all means it is fine with me to put your results up on the forum for others to see.

Cheers,
Bob
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Old 13th February 2011, 03:26 PM   #1488
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Originally Posted by Olivier73 View Post
Hi Bob,

I am using a complementary IPS & VAS. On one side I think it's too much components and too much potential interference to have just an led indication but on the other hand, the used amplifier topology is very complex so it doesn't come to one or two more components... I am unsure what to do for now.
But I choose not to go that road for now, the led can come in later when the circuit proto works in reality.

As you know I have to tame the fighting VAS Iq. I use a CMCL for it which seems to work well in simulation and also in reality for some part (that is in my circuit). My major problem for now is that my phase lag grows faster than it should with rising frequency.

I will redesign my pcb because I hope it suffers PCB layout problems such as : parasitic capacitors. One that bothers me much is the node between the IPS output and VAS input (on both sides). All summed this track is very long because it connects many components : Q mirror, Q diff, IPS clamp diode, VAS input Q, RC filter to rail, CMCL Q, protection Q, VAS clamp diode, compensation circuit.
Not only the length of the track is an issue but its impedance value must probably play a role as well as the amount of connections it has...

Do you think my trouble could have its origin on the pcb? Or is its impact usualy soo small I should search elsewere....

Is there a particular point to keep in mind?

Cheers,

Olivier
Hi Olivier,

I'm sorry I did not get back to you sooner on your question. I'm a little skeptical that the problem is the length or layout of that PCB trace, but it is true that there are a lot of potential sources of capacitance hanging on that node. I'm not an expert on CMCL, and so don't know what role if any it is playing here. As you know, I use a different approach in my book to cure the fighting VAS problem in this topology.

Are you using two Miller comp capacitors, each from output to input of the VAS? If the design is such that their value is small (e.g., less than, say, 30 pF), then a large amount of stray capacitance hanging on the VAS input node might bother the circuit. Do these concerns show up in simulation or just in a real amplifier?

Cheers,
Bob
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Old 14th February 2011, 08:06 AM   #1489
godfrey is online now godfrey  South Africa
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Hi Bob
Thanks for the feedback
Quote:
Originally Posted by Bob Cordell View Post
What power transistor models were you using?
I'm not quite sure I just used LTSpice to run the .asc file extracted from the zip file you supplied, then added another pair of the same output devices already used.

Checking now, I see there's an include command, so presumably it used the MJL21193C/MJL21194C models from your text file.
Quote:
Originally Posted by Bob Cordell View Post
However, it is always important to bear in mind that more paralleled devices means more capacitance to drive for the driver ...
I was surprised recently, when poking about the internal workings of an amp sim, to find that 2 pairs of thermaltrak output devices presented a load of almost 1nF to the driver stage, with no load on the output. A quick look at the datasheets confirmed your models got that about right.

The real shocker was the amplitude and waveforms of the drivers' base currents with high frequency high power output - much worse than expected.

It's quite astonishing how badly mangled the internal waveforms have to be to achieve a clean output from a class AB amp under those conditions.
Quote:
Originally Posted by Bob Cordell View Post
...it is also often wise to use Baker clamps or something similar to prevent the output transistor bases from ever getting closer than, say, 5V from the rails...
Interesting ideas there. How bad the penalty is depends on how you look at it. If you start with the intent to use a 25-0-25 mains transformer, it could mean 35 instead of 50 watts output, and seem like a really bad idea.

OTOH, if you start with the idea of building a 50 watt amp, it just means you'll have to use a slightly bigger transformer (maybe 28-0-28) and a little extra heatsink, for negligible extra cost.

I think the awkward bit is ensuring that the rail voltage never dips below the clip voltage, which means giving extra attention to psu droop etc. Ideally it would be nice to clip at a fixed voltage but that's probably not practical due to uncertainty regarding the line voltage (and hence rail voltage).

Do you set the clip voltage relative to the rail voltage (e.g. 90% of rail, or rail - 5V), and then just filter it to get rid of ripple? If so, what sort of time constant would you recommend?

My concern is that we want to effectively filter the 100/120Hz ripple, but don't want VLF variations to be attenuated or badly phase shifted. e.g. When playing loud 90bpm music, the rail voltage will be varying at 1.5 Hz and, depending on house wiring, the line voltage can also suddenly drop when other power-hungry appliances are switched on.

Cheers - Godfrey
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Old 14th February 2011, 08:33 AM   #1490
dadod is offline dadod  Croatia
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Default Thermaltrak stability

Hello Bob,
I would appriciate your comment on ThermalTrak+TMC tread.
I tried to follow your advice how to implement a bias current stability and if you can take a look to this tread.
ThermalTrak+TMC amp
thank you in advance
Damir
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