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Old 25th June 2010, 06:17 AM   #1
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Default Help with diff Amp current balance

Hi All,

Just wondering if I could get a couple of pointers regarding the balance of current through the two diff amp arms in this fairly standard design I'm working on. I am only starting out at amp design and I have Douglas Self's book handy but I can't seem to work out why the current is significantly different.
From spice (LTSpice) it is saying R12 & R20 have equal current at around 220u each. Current through R19 is not much different. Problem is R18 has around 300u which goes through Q13 and then around 80u is shunted off to the Vas base Q8. Is this normal? Should I just up the total current through the two arms so as to make the difference less significant? I understand there might be a few issues with this amp (there usually is) and so any suggestions would be appreciated.
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Old 25th June 2010, 10:43 AM   #2
AndrewT is offline AndrewT  Scotland
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to get the balance you want and what Self says is important to get the best out of an LTP you need the currents in R18 and R19 to be identical.

With a mirror load you cannot trim R17 to balance your currents.
Nor can adding a degeneration resistor to the VAS work to improve balance.

Look at your mirror.
Base current for each of the two transistor is ~ Ir19/hFE and [Ir18-Ibq8]/hFE
Both these base currents are supplied through R19.

If the total of the 2base currents exactly equals the base current going to Q8 then you will find that your currents are balanced.

Look at hFE of the VAS to determine what is needs as a base current.
Work from there.

There is a further adjustment.
Add a resistor from the junction of the bases of Q9&Q10 down to the negative supply rail.
This resistor can be ~47k to 2M2 depending on what value of extra current you want to pull through R19. This could even be a 1M trimmer.
Do NOT trim the 100r emitter resistors of the mirror.
Match all the equal resistors to <0.1%
Match the LTP and the Mirror transistors for both hFE and Vbe at the expected operational current. A DMM cannot do this.
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Old 26th June 2010, 02:12 AM   #3
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Thanks for your help Andrew.
I realise now that the Q8 (Vas) base current was required to be 80uA if I continued to use the default NPN transistor in LTspice which had a hfe of 100. Changing to a 2N2222 (the first one I saw in the transistor library) with a much higher hfe lowered that base current to around 33uA. This was for a Vas collector current of 8mA (I have no idea at the moment whether this too high or low).
This change lowered I(R18) and after I added your suggested 47k resistor from mirror current transistor bases to negative rail it pulled an extra 10uA from R19.

This has brought the two currents to just below 10uA difference with I(R19) still the lower of the two. =not bad

However it seems to me when I go ahead and change the mirror current transistors from the default npn (hfe=100) to higher beta ones this differnece will be made larger again!

Seems to me these are my options to lower I(R18) and/or up I(R19):
- Pull less current through the VAs collector
- Make your suggested resistor pull even more extra current from R19 (is there some limit here?)
- Make the hfe's of Q1 & Q2 (current mirror) lower as to pull more current from R19(this doesn't seem like the way to go for good current mirror performance but I have no basis for this argument!)
- Read page 125 in Self's book and realise that an emitter follower config for the Vas stops this problem!

I tried the the emitter follower method for the Vas and it indeed pulled much less current from the Diff Amp arm and thus I have been able to achieve current balance! Yay!
Now to work out what devices to use taking into consideration gm of the diff amp, dominant polls and all that gain linearisation fun.
This amp design thing is actually quite fun once you start getting somewhere!
Design so far if anyone wants to comment feel free...
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Old 26th June 2010, 08:31 AM   #4
AndrewT is offline AndrewT  Scotland
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now that you see and understand why and how these various devices and component values affectthe LTP balance.
Here's the easy way, from GK,
VAS gain and mirror gain have equal hFE.
VAS current = sum of mirror currents.

Simply select hFE for the matching mirrors and select similar hFE for the VAS.

If you can't get a precise match then altering the VAS current gives you the adjustment necessary. Often to get the best performance from the VAS it's current must be way off sum of mirror currents.
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Old 28th June 2010, 11:17 AM   #5
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Quote:
Originally Posted by AndrewT View Post
now that you see and understand why and how these various devices and component values affectthe LTP balance.
Here's the easy way, from GK,
VAS gain and mirror gain have equal hFE.
VAS current = sum of mirror currents.

Simply select hFE for the matching mirrors and select similar hFE for the VAS.

If you can't get a precise match then altering the VAS current gives you the adjustment necessary. Often to get the best performance from the VAS it's current must be way off sum of mirror currents.
To minimize thermal drift effects I recommend additional at least 3mA through each LTP half, that means, the associated current source needs 120 ohms for R17 in the emitter line (700mV : 6mA ~ 120). Lower currents there are also not good for the sonic quality except when you use jFETs.

Last edited by tiefbassuebertr; 28th June 2010 at 11:22 AM.
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Old 28th June 2010, 11:47 AM   #6
AndrewT is offline AndrewT  Scotland
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Quote:
Originally Posted by tiefbassuebertr View Post
To minimize thermal drift effects I recommend additional at least 3mA through each LTP half,
does it?

The extra heat dissipation means that the devices take longer to reach operating temperature and the ambient will now be higher than for the low dissipation, so now the ambient takes longer to reach operational temperature. During this phase the input devices are still rising in temperature tracking the changing ambient temperature. That to me does not equate to
Quote:
to minimise Thermal Drift effects
Now let's look at room temperature. It varies. we see from the above paragraph that the case temperature and the device temperature tracks with ambient temperature whether of the low or high dissipation version.

If ambient temperature rises then the device temperatures must also rise.
Now look at the temperature rise with ambient in the low dissipation case and compare the temperature rise with ambient in the high dissipation case.
I suspect it can be shown the the two temperature rises are the same. The devices try to track the ambient temperature.

Now we move to device parameters.
Let's assume that the low dissipation device operates at 10Cdegrees above ambient and that the high dissipation device operates at 20Cdegrees above ambient.
Let's take two different Ta conditions of 20degC and 30degC.

The low dissipation device will operate at 30degC and 40degC for these two ambients.

The high dissipation will operate at 40degC and 50degC for the same two ambient conditions. Convert those to absolute temperatures and then convince me that the high dissipation version is more thermally stable.
Now tell us how long the low dissipation takes to reach thermal stability and how long the high dissipation takes to reach thermal stability.

I think I will always go for the lowest operating temperatures when ever there is choice.
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Old 28th June 2010, 02:09 PM   #7
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Originally Posted by AndrewT View Post
does it?

The extra heat dissipation means that the devices take longer to reach operating temperature and the ambient will now be higher than for the low dissipation, so now the ambient takes longer to reach operational temperature. During this phase the input devices are still rising in temperature tracking the changing ambient temperature. That to me does not equate to

Now let's look at room temperature. It varies. we see from the above paragraph that the case temperature and the device temperature tracks with ambient temperature whether of the low or high dissipation version.

If ambient temperature rises then the device temperatures must also rise.
Now look at the temperature rise with ambient in the low dissipation case and compare the temperature rise with ambient in the high dissipation case.
I suspect it can be shown the the two temperature rises are the same. The devices try to track the ambient temperature.

Now we move to device parameters.
Let's assume that the low dissipation device operates at 10Cdegrees above ambient and that the high dissipation device operates at 20Cdegrees above ambient.
Let's take two different Ta conditions of 20degC and 30degC.

The low dissipation device will operate at 30degC and 40degC for these two ambients.

The high dissipation will operate at 40degC and 50degC for the same two ambient conditions. Convert those to absolute temperatures and then convince me that the high dissipation version is more thermally stable.
Now tell us how long the low dissipation takes to reach thermal stability and how long the high dissipation takes to reach thermal stability.

I think I will always go for the lowest operating temperatures when ever there is choice.
You are right, if there are designs without dissipation limiting resistors in the collector lines from the differential amp (like attached design from NAD 306 - and consequently dark burned PCB aera arround Q401/Q403 cause +/-80V and high dissipation).
But I am right, if there are still such resistors in use (20 - 25 volts Uce is a good choise).
You get now additional advantage cause the possibility to use input BjT's without "MPSA-42 like" high max Uce voltage - each 40V Uce type can be use.
By my modification work at high voltage audio amps I still enhance the current arround 3-10 mA/each half of diff input pair (independend of the transistor types) and introduce the resistors in the collector line - this will get still better sonic results so as better offset stability, if no offset servo is present.
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Last edited by tiefbassuebertr; 28th June 2010 at 02:21 PM.
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Old 28th June 2010, 03:05 PM   #8
AndrewT is offline AndrewT  Scotland
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you have shown a folded cascode on half the LP.
The voltage at the emitter of the cascode is ~1.2V less than the supply rail. This is the voltage at the collector of that half of the LTP. This determines the Vce of the LTP. The other half of the LTP has full rail voltage defining Vce.
How does the dissipation in the two halves of the LTP stay the same if you increase the tail current?
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Old 28th June 2010, 06:24 PM   #9
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Quote:
Originally Posted by AndrewT View Post
you have shown a folded cascode on half the LP.
The voltage at the emitter of the cascode is ~1.2V less than the supply rail. This is the voltage at the collector of that half of the LTP. This determines the Vce of the LTP. The other half of the LTP has full rail voltage defining Vce.
How does the dissipation in the two halves of the LTP stay the same if you increase the tail current?
By this amp I don't perform variations to increase the tail current, because there are already 3,5mA present.
R421, R427 and R423 determines the currents through the LTP/folded cascode (700mV : 100R = 7mA : 2 = 3,5 mA). Q401/403/411/413 = 3,5mA/each and 7 mA for Q407,405 and 409. By this amp only two 10K resistors I must introduce (and 2xBC549C for the burned 2SC2240).
Please note - this circuit don't comes from me; it's in the showed version a not modified NAD design.

Last edited by tiefbassuebertr; 28th June 2010 at 06:27 PM.
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Old 28th June 2010, 10:01 PM   #10
AndrewT is offline AndrewT  Scotland
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How about posting the appropriate schematic for us to discuss?
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