HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles

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Hello there everyone,
I am trying to build a Randy Slone Mirror Image Topolgy Amplifier. More specifically one like on page 354 figure 11.14. In a nutshell it represents a dual differential input stage with current mirrors. These two input stages are DC coupled to the VA stage which consists on the POS side and the NEG side of a darlington setup and tied together through two cascoded BJT's. I didn't built the OPS yet. I close the loop from there.
I Built,allready 3 PCB's with different layouts. I must have blown hundreds of 2N5551 2N5401 2SB649 and 2SD669's!
I am deeply discouraged...
What is it?
I am 100% sure there are no goofs in the nodes nor in the component mounting.
Is the PCB layout still wrong? Is my lab powersupply rotten? Is my grounding rotten?
But it very rarely works and when it works it seems very very delicate. The slightest manoeuvre puts it in lockout or Power Supply safety or worse sends some BJT's to heaven.
I hereby send the schematic based on Slones designs.
What I often have :
The output goes to the railsupply + or - and one power supply + or - goes into protection at 150mA or 200mA but raising to 1A it still shows RED.
If the output is at 0VDC the last stage part (VAS) is not active. No bias current flowing -> Class C opration.
Heavy Oscillations making the power supply clicking in and out of protection like nuts.
Once it worked quite well : however the VAS Iq was about 65mA with 60V rails this puts the 2SB669 and 2SB649 close to the edge. They go very hot. The output was not realy good. It was when the feedback was really large and the miller caps 5 times too high (500pF)...Slew Rate was only about 15V/us and BW 40kHz or so ... but anyway it stil behaved unstable (I cannot belive it has to do with nyquist instability it must be something else ... more parasitic i think). For example when I want to measure with a portable V meter touching one probe to the circuit causes it to go in protection and sometiomes comes out again but sometimes i need to power off and on again. Or it takes 10 seconds for the circuit to restore (cap charge discharge?).
I feel uncomfortable to tell I am struggling allready years and now I feel out of options ...
Can someone step up for me? :)
Initiate a conversation to help me?
Everything is welcome

I noticed that the VAS Iq is very very sensitive to the current mirror degeneration resistors. A small inbalance and everything goes to saturation or cutoff of crazy stuff...

Is the schematic Slone designed just that hazardous and one needs fiddling like hell? I cannot believe it...

Anyonez??:confused::confused::confused::confused::confused::confused::dunno::dunno::dunno::dunno::hypno2::hypno2::hypno2::hypno2::hypno2::hypno2:
 

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The reason for your confusion is that there is a design flaw in this topology. The input stage is bogus. It does, in the mathmatical sense, have an 'undefined' variable in the transfer function. The problem is that there is an undefined bias current in the VAS transistors. I still don't know why this circuit is still out there, but a simple fix is to replace the two current mirrors with resistors. The current mirror load for a single LTP driving a single end VAS loaded with a resistor/bootstrap/CCS has the VAS bias current defined by such load. But since this VAS is complementary, one depends on the other for its bias reference. With the mirrors replaced by resistors in the complementary input stage, the VAS transistor bias current is defined by the input stage current, ie the voltage across the collector (of the two complementary input transistors) resistors.;)
 
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Try to split R6, R9 to serial conection of two resistors about 22ohms, and conect emitors Q13,Q16 to new "midpoints" of R6,R9, remove R26, R27...It will work reliable, with stable currents and very good performance.
 
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Hello guys,

thnx for all your replies

I will certainly try the split of the degeneration resistors on the right current mirror transistors.
I can always try with resistive collector loads too and scrap the current mirrors.
But I have a question here... I certainly accept the fact that the VAS Iq is undefined and that therefore the output clips to the rail + or - or that the VAS is cutt-off or saturated. Lets say the DC setting/setup is very cumbersome and is a matter of goodluck with component tolerances and takes a lot of time and money (considering smoked Q's) ... but eventually the undefined item comes out at a nice point that sets the Iq to an acceptable value...
Why do I get RF oscillations or other funny stuff driving the powersupply to protection???
Another funny thing about the schematic is that an AC analysis shows something strange in the HF roll-off. Lets say HF roll-off starts @ 250kHz and comes to 0dB at 20MHz where the phaselag is still less than 150deg (which shows nyquist = OK). But further on at exactly 100MHz there is a gain spike (very very sharp) showing 25dB of gain.this is because at just under 100Mhz the phaselag is 180° but the gain is -14dB it shouldnt be a problem? Why does it go up so hard? I always thought this might be due to all the poles of the transistors are at the same point in the simulation .
(i removed the phase forward circuit from previous design that is c11 r28)
i send hereby the graph....
Anyway another question : now that i think of it, isn't it dangerous to still have gain in the MHz range even if phase lag is ok? Is it possible that a 5mhz signal which is still with gain gets to the positive input through poor design of pcb ... sort of capacitive coupling to the + input? (but where does the 5mhz starts from?? harmonics?) if this is the case it becomes nyqist unstable since the phaselag being smaller than 180 but sent to the + through unwxanted ac coupling? BBut it will also to the neg input right? how this behave?

I resent the schematic with c11 & r28 scrapped for clarity and added the ac analysis

I hope you guys can follow my braindump here :)

:deer: HIT ME :)
 

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Hi BV,
I tried your suggestion but i am not sure if i understood well? it means my VAS will be supplied/powered by a fraction of a curent mirror leg current instead of the power rails? It's odd looking on the schematic. Strangly the transient simulation seems to show something working... the ac analyses is more strange. hf rollof starts at 100k but levels off at half gain and goes flat till 10mhz then down again to unity around 50mhz. nyqist instability shows up at 2mhz (at half gain) where phase lag reaches -180°
You seem to have added a zero in the plot at 1mhz...
did i understand something wrong?
best regards
 
Oliver,

why do you care about the ac analysis when even dc operation fails? Remove Q1, Q4, Q5, Q8, recalculate the operating points and modify the necessary resistor values. Omit R24 and R25. R26 and R27 should also have a much higher value. In this way you have a basic amplifier which should have stable operating points. In my opnion you can also get rid of Q11 and Q12.
 
Yes, there is no point in worring about the AC domain if the DC is not correct. It doesn't matter if by some strange lucky guess the bias seems to work, as the temperature of the transistors change, so will variables like Vbe, Hfe. Simulators don't use real components that produce real heat. There has to be some DC reference that sets the VAS bias current. Forget the mirror loads for the input stage. As Bocka said, forget Q11 & Q12. There is plenty of current gain in Q13 & Q16. 3mA per leg is fine for the input stage, so collecor resistors of 240 Ohms will give you about 0.7V that you need to drive the base of Q13 & Q16. Forget R24 & R25 you don't need them.
Make R26 & R27 10 - 47 Ohms. Remember 0.6V from emitter to base of Q13/16, so roughly 0.1V/R26(27) will determain the VAS current. Any mismatch in DC output voltage will be adjusted via the nf loop.
100pf seems quite large for C9 & C10. When the DC realm works, adjust these to a smaller value to increase the compensation rolloff frequency.:)
 
So, here is it as promised..
 

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Thank you for the schematic I will study your layout and try to understand why this should work better. Did you built one of these topologys?
What I also will do is to simulate with the remarks of the other guys since there seem to be more people against this topology than for.
There is still one thing that puzzles me! If the topology contains an ill defined variable like the Iq of the VAS. Lets say the DC settling can come out : Vout to rail voltage, VAS cutoff completely, VAS Iq too high, etc... but it could by luck be right. I agree that even if it comes out right it might or will still run away to the afore mentionned settings (VAS cutoff, etc...). But if it is a DC problem I would guess the amp would become anyhow locked in some position even if not the wanted one.
But mine often goes flipping around and the protection goes clicking like hell. The only reason for that i can come up with is that by going into protection the input dc condition changes as one of the rails drop severely since it now oprates in constant current mode (max Iout as setup and output voltage reduces to maintain imax) it often means the amp gets eg +60V and -10V only. This could on his turn unlock the amp from its bad condition and go into another bad one causing the powersupply to slip out of its protection which causes then again the previous situation and so on... Do you guys agree this it what happens or is it something else?
If this is not true i must conclude i have an AC problem which for me can be 3 things : 1) nyquist instability (i dont believe), 2) ground loops or 3) rf pick up and/or airborne feedback to the non inverting input of the diff amp.
My problem can surely also be a combination which would put me even further from home :)
Ok let's go try !
untill later ...
 
Fast Comparison between my layout called BASE and BV's one called BV_MOD

BASE :
Itail IS : 4,6mA
Iq VAS : 2,6mA
Slew Rate : 133V/us (with 33pF as Miller cap only)
CL Gain : 35dB
HF r/o : 772kHz (this is a bit high no?)
Phase @ 0dB : -150 deg

BV_MOD:
Itail IS : 4,6mA same
Iq VAS : 7,2mA quite higher
Slew Rate : 120V/us (with 33pF as Miller cap only) slightly lower but irrelevant
CL Gain : 34.7dB slightly lower but irrelevant
HF r/o : 660kHz (still this is a bit high no?) slightly lowel but irrelevant
Phase @ 0dB : -150 deg idem

Basicly they perform the same way.
I still have a hard peak at 100Mhz in the AC analyses (still waiting for someone to tell me why)

There is one big difference in behavior however :
When I change either one of my current mirror degeneration resistors its effect on IQ VAS is tremendous. A 1% change in value (considering 1% tol resistors it is real) causes the IQ VAS to from 3mA to nearly 0 or otherwise to 30mA 10x higher.
In the BV_MOD layout the same 1% change does vary IQ VAS by not more than a few % mayb +/- 3%.

THIS IS A VERY INTERESTING FIGURE AND MUST GREATLY INCREASE DC STABILITY !
I suppose this is due to the fact that IQ VAS is now imposed b y something else than in the base circuit and this something new must be DEFINED. Can you tell me quickly what it is?

The same thing applies when changing the DEGEN resistors of the DIFF Q's. In the base its effect is also tremendous on VAS IQ. In the BV_MOD layout not at all.

One thing remains to be checked. What are the THD results of both layouts?

Source : 1KHZ 1Vpp sine input

BASE : 0,002262%
MOD_BV : 0.001294% much better !!??

With a little remark that BASE is mostly 2nd order lets say 85% and in BV-MOD 50-50 2nd and 3rd order. However I should remake the first test to see absolute values as it could be that since total is a lot lower that 3rd is equal and that 2nd has been reduced causing the total to be reduced...

I must go for a concert now ... i am late damn :)

I will keep learning :)

Greetz
 
Hi Bv,
What do you think of Slone's two pole compensation? Usefull or just complicating?
Instead of using 1 miller cap of lets say 33pF he places one of lets say 330pF in series with the 33pF one. The bigger one comes from the VAS output and the smaller one couples back to the VAS input. Between both he connects one end of a resistor which goed back to the rail supply. This is done on both sides of the Mirror Image.

What dou you think of his FEEDFORWARD circuit? It consists of a cap and a resistor in series (eg 15pF and 330ohm) the circuit is parallel over the feedback resistor (10K in my circuit). This FF circuit was not yet implemented in the circuit I put on this forum...

Can you tell something about this?

Thnx

Olivier
 
stupid VAS

Hi Olivier,

Here you can find more on this subject:http://www.diyaudio.com/forums/solid-state/16796-unstable-vas-current-amp-slone-book.html#post195526

and here one of the possible solutions, a common mode control loop (CMCL): MCP Front-End
See: Q5, Q10, Q11 & Q12. This is the most simple implementation of a CMCL (could be done better, but cost 8 additional trannies instead of 4).
Somewhere on this forum, you can also found a CMCL based on an opto-coupler.
BTW, don't build that MCP amp, as it is obsolete by now.
 
Hoi Edmond Stuart,
Did you check BV's modification to my base circuit? He splits one of the degenaration resistors of the Current Mirrors then instead of feeding the VAS directly by the rail voltage it gets its current through one of the split resistors in the CM circuit. Is this just another method of CMP (simple one) or is this a completely different approach? And which is best?
Thnx for the circuit anyway. When you say CMP is obsolete you mean the optocoupler thing right? Or do you mean the Slone Amp?

Is it a good idea to use slones approach and try to eliminate the VAS stability problem by any means or does any attempt to coop with the problem reduces the whole concept to something worse than other - simpler circuits?

Would you build Slones one like I try (with needed mods)?

Beste Groeten,

Olivier
 
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