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-   -   HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles (http://www.diyaudio.com/forums/solid-state/165530-heeeelllppp-m-randy-slone-mirror-image-topology-construction-troubles.html)

Olivier73 21st April 2010 09:13 PM

HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles
 
1 Attachment(s)
Hello there everyone,
I am trying to build a Randy Slone Mirror Image Topolgy Amplifier. More specifically one like on page 354 figure 11.14. In a nutshell it represents a dual differential input stage with current mirrors. These two input stages are DC coupled to the VA stage which consists on the POS side and the NEG side of a darlington setup and tied together through two cascoded BJT's. I didn't built the OPS yet. I close the loop from there.
I Built,allready 3 PCB's with different layouts. I must have blown hundreds of 2N5551 2N5401 2SB649 and 2SD669's!
I am deeply discouraged...
What is it?
I am 100% sure there are no goofs in the nodes nor in the component mounting.
Is the PCB layout still wrong? Is my lab powersupply rotten? Is my grounding rotten?
But it very rarely works and when it works it seems very very delicate. The slightest manoeuvre puts it in lockout or Power Supply safety or worse sends some BJT's to heaven.
I hereby send the schematic based on Slones designs.
What I often have :
The output goes to the railsupply + or - and one power supply + or - goes into protection at 150mA or 200mA but raising to 1A it still shows RED.
If the output is at 0VDC the last stage part (VAS) is not active. No bias current flowing -> Class C opration.
Heavy Oscillations making the power supply clicking in and out of protection like nuts.
Once it worked quite well : however the VAS Iq was about 65mA with 60V rails this puts the 2SB669 and 2SB649 close to the edge. They go very hot. The output was not realy good. It was when the feedback was really large and the miller caps 5 times too high (500pF)...Slew Rate was only about 15V/us and BW 40kHz or so ... but anyway it stil behaved unstable (I cannot belive it has to do with nyquist instability it must be something else ... more parasitic i think). For example when I want to measure with a portable V meter touching one probe to the circuit causes it to go in protection and sometiomes comes out again but sometimes i need to power off and on again. Or it takes 10 seconds for the circuit to restore (cap charge discharge?).
I feel uncomfortable to tell I am struggling allready years and now I feel out of options ...
Can someone step up for me? :)
Initiate a conversation to help me?
Everything is welcome

I noticed that the VAS Iq is very very sensitive to the current mirror degeneration resistors. A small inbalance and everything goes to saturation or cutoff of crazy stuff...

Is the schematic Slone designed just that hazardous and one needs fiddling like hell? I cannot believe it...

Anyonez??:confused::confused::confused::confused:: confused::confused::dunno::dunno::dunno::dunno::hy pno2::hypno2::hypno2::hypno2::hypno2::hypno2:

mlloyd1 21st April 2010 09:27 PM

you are not alone. a search might lead you here:
http://www.diyaudio.com/forums/solid...t-mirrors.html

mlloyd1

homemodder 21st April 2010 09:32 PM

Im afraid youll have to scrap that design and build something else, that design will not work, try his optimos amp, great amp.

bocka 21st April 2010 09:37 PM

The schematic is wrong as the voltages on node 14 and 15 are undefined and so the current across the output transistors is. I'd assume your output transistors Q11, Q12, Q13, Q14, Q15 and Q16 will blow? To me it looks that the schematic is a spice engineered one

CBS240 22nd April 2010 02:06 AM

The reason for your confusion is that there is a design flaw in this topology. The input stage is bogus. It does, in the mathmatical sense, have an 'undefined' variable in the transfer function. The problem is that there is an undefined bias current in the VAS transistors. I still don't know why this circuit is still out there, but a simple fix is to replace the two current mirrors with resistors. The current mirror load for a single LTP driving a single end VAS loaded with a resistor/bootstrap/CCS has the VAS bias current defined by such load. But since this VAS is complementary, one depends on the other for its bias reference. With the mirrors replaced by resistors in the complementary input stage, the VAS transistor bias current is defined by the input stage current, ie the voltage across the collector (of the two complementary input transistors) resistors.;)

BV 22nd April 2010 07:53 AM

Try to split R6, R9 to serial conection of two resistors about 22ohms, and conect emitors Q13,Q16 to new "midpoints" of R6,R9, remove R26, R27...It will work reliable, with stable currents and very good performance.

Olivier73 22nd April 2010 08:24 PM

2 Attachment(s)
Hello guys,

thnx for all your replies

I will certainly try the split of the degeneration resistors on the right current mirror transistors.
I can always try with resistive collector loads too and scrap the current mirrors.
But I have a question here... I certainly accept the fact that the VAS Iq is undefined and that therefore the output clips to the rail + or - or that the VAS is cutt-off or saturated. Lets say the DC setting/setup is very cumbersome and is a matter of goodluck with component tolerances and takes a lot of time and money (considering smoked Q's) ... but eventually the undefined item comes out at a nice point that sets the Iq to an acceptable value...
Why do I get RF oscillations or other funny stuff driving the powersupply to protection???
Another funny thing about the schematic is that an AC analysis shows something strange in the HF roll-off. Lets say HF roll-off starts @ 250kHz and comes to 0dB at 20MHz where the phaselag is still less than 150deg (which shows nyquist = OK). But further on at exactly 100MHz there is a gain spike (very very sharp) showing 25dB of gain.this is because at just under 100Mhz the phaselag is 180 but the gain is -14dB it shouldnt be a problem? Why does it go up so hard? I always thought this might be due to all the poles of the transistors are at the same point in the simulation .
(i removed the phase forward circuit from previous design that is c11 r28)
i send hereby the graph....
Anyway another question : now that i think of it, isn't it dangerous to still have gain in the MHz range even if phase lag is ok? Is it possible that a 5mhz signal which is still with gain gets to the positive input through poor design of pcb ... sort of capacitive coupling to the + input? (but where does the 5mhz starts from?? harmonics?) if this is the case it becomes nyqist unstable since the phaselag being smaller than 180 but sent to the + through unwxanted ac coupling? BBut it will also to the neg input right? how this behave?

I resent the schematic with c11 & r28 scrapped for clarity and added the ac analysis

I hope you guys can follow my braindump here :-)

:deer: HIT ME :)

Olivier73 22nd April 2010 08:46 PM

Hi BV,
I tried your suggestion but i am not sure if i understood well? it means my VAS will be supplied/powered by a fraction of a curent mirror leg current instead of the power rails? It's odd looking on the schematic. Strangly the transient simulation seems to show something working... the ac analyses is more strange. hf rollof starts at 100k but levels off at half gain and goes flat till 10mhz then down again to unity around 50mhz. nyqist instability shows up at 2mhz (at half gain) where phase lag reaches -180
You seem to have added a zero in the plot at 1mhz...
did i understand something wrong?
best regards

bocka 22nd April 2010 09:13 PM

Oliver,

why do you care about the ac analysis when even dc operation fails? Remove Q1, Q4, Q5, Q8, recalculate the operating points and modify the necessary resistor values. Omit R24 and R25. R26 and R27 should also have a much higher value. In this way you have a basic amplifier which should have stable operating points. In my opnion you can also get rid of Q11 and Q12.

CBS240 22nd April 2010 09:37 PM

Yes, there is no point in worring about the AC domain if the DC is not correct. It doesn't matter if by some strange lucky guess the bias seems to work, as the temperature of the transistors change, so will variables like Vbe, Hfe. Simulators don't use real components that produce real heat. There has to be some DC reference that sets the VAS bias current. Forget the mirror loads for the input stage. As Bocka said, forget Q11 & Q12. There is plenty of current gain in Q13 & Q16. 3mA per leg is fine for the input stage, so collecor resistors of 240 Ohms will give you about 0.7V that you need to drive the base of Q13 & Q16. Forget R24 & R25 you don't need them.
Make R26 & R27 10 - 47 Ohms. Remember 0.6V from emitter to base of Q13/16, so roughly 0.1V/R26(27) will determain the VAS current. Any mismatch in DC output voltage will be adjusted via the nf loop.
100pf seems quite large for C9 & C10. When the DC realm works, adjust these to a smaller value to increase the compensation rolloff frequency.:)


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