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Old 18th November 2011, 09:45 PM   #371
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Thumbs up Testing

Hi Edmond,

Hereby you find the schematic and AC analyses result for the millerloop testing. I also see the gain is much lower. The CMCL testing is perfect. It follows the same slope and format.

I have 6 fets of each channel (N/P) so I could go up to 6 parallel legs. Mono off-course. But I will need more if I want to build the final amplifier anyway. I would say lets make it 4 or 5 legs (not 6 as one could die by mistake during experimenting, and I am optimistic). I bought them throug a Dutch online shop (don't remember the name however - could look it up).

I will use the actual PCB as front-end (sure) but only for the experimentingfase. Later on I will indeed optimize it (with your help if you wish) with input zobel, filter, etc. Anyway the dummy OPS is embedded in the current PCB and for the final amplifier I would like not to have this dummy OPS on it anymore. It will also need some fusing by the way. Maybe (probably) also some tracklayout upgrades.

By more stable current sources for the LTP you refer to the zener regulated ones right? At a voltage where the zener has a near 0 temperature coefficient? Isn't that solution less regulating than a 2 Q solution?

I will stay put at 10ppm and not go much further as I don't want to go nuts on the wiring and PCB track lay-out. Also I want it to be very stable and rugged, but I already said that.

As promised Vgs comes up tomorrow. I found a testing procedure on the net. Hope it works

Cheers,

Olivier
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Old 18th November 2011, 10:10 PM   #372
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Oops. Forgot to attach the files.
Here they are :

Good Night.
Attached Files
File Type: pdf millerlooptst_AC.pdf (21.4 KB, 30 views)
File Type: pdf millerlooptest_sch.pdf (23.3 KB, 57 views)
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Old 19th November 2011, 03:00 PM   #373
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Quote:
Originally Posted by Olivier73 View Post
Hi Edmond,

Hereby you find the schematic and AC analyses result for the millerloop testing. I also see the gain is much lower.
Hi Olivier,

I don't know why, but clearly something went wrong. Please try my MC9 files instead (seen below).

Quote:
The CMCL testing is perfect. It follows the same slope and format.

I have 6 fets of each channel (N/P) so I could go up to 6 parallel legs. Mono off-course. But I will need more if I want to build the final amplifier anyway. I would say lets make it 4 or 5 legs (not 6 as one could die by mistake during experimenting, and I am optimistic). I bought them throug a Dutch online shop (don't remember the name however - could look it up).
I hope you can get some more.

Quote:
I will use the actual PCB as front-end (sure) but only for the experimentingfase. Later on I will indeed optimize it (with your help if you wish) with input zobel, filter, etc. Anyway the dummy OPS is embedded in the current PCB and for the final amplifier I would like not to have this dummy OPS on it anymore.
What's the problem? You only have to omit seven tiny components. Besides, nobody sees it anyhow (in a closed cabinet).

Quote:
It will also need some fusing by the way. Maybe (probably) also some track layout upgrades.
If you put the OPS on a separate PCB, you can put the protection stuff on there too.


Quote:
By more stable current sources for the LTP you refer to the zener regulated ones right? At a voltage where the zener has a near 0 temperature coefficient? Isn't that solution less regulating than a 2 Q solution?
The point is that the 2Q configuration has a quite large tempco, which not only has an effect on the LTP, but also on the VAS and in the end on the bias current of the OPS.
Therefore I was thinking of a more stable CCS, based on a voltage reference (ZR431) plus a diode to compensate for the Vbe tempco. Besides, the same circuit can also bias the base of the cascode tranny.
For the time being, you can use 6V2 Zeners instead of 1k Rs in the CMCL circuit. All other Zeners are 4V7 and should be supplied with (roughly) the same amount of current.

Quote:
I will stay put at 10ppm and not go much further as I don't want to go nuts on the wiring and PCB track lay-out. Also I want it to be very stable and rugged, but I already said that.
If Vcc = 63V, RL = 8 Ohms, Vout = 50Vpk, THD20 = 14ppm. BUT ... I think this figure is a bit pessimistic due to bad models of the MOSFETs. See the jagged residual (4th pic), which is highly unnatural. This is the result of discontinuities in the derivatives of the mathematical model.

Quote:
As promised Vgs comes up tomorrow. I found a testing procedure on the net. Hope it works
Cheers,
Olivier
Below a new version using the current PCB plus a preliminary OPS. This one is equipped with separate push-pull drivers for the top- respectively bottom-MOSFETs (yes indeed, that's my favorite configuration ). But we have a problem in case of very low threshold fets (i.e. laterals), as the minimum differential OP voltage (between G1 and G2) of this kind of setup is >= 2*Vbe. That's too much for the laterals. By 'overlapping' the drivers 'voltage-wise' (sorry for my Dunglish) I was able to reduce aforementioned voltage to a range of 250 .... 1500mV. (notice C23 and Q29, they are placed 'upside down')
BTW, this configuration can easily be modified to fit higher threshold fets, by means a few jumper. More on this later.

One point of caution: Don't torture the drivers with an unfiltered square wave, as peak currents will destroy them (most likely). In order to safely test the amp, you will need a second order LP filter at the input.

Probably you will have a lot of questions about this design, as it is a bit unusable. But first, let's get the Miller sim working.

See you tomorrow.
E.
Attached Images
File Type: png RS10-MillerLoop.png (61.2 KB, 205 views)
File Type: png RS10-front-end.png (53.2 KB, 201 views)
File Type: png RS10-OPS.png (44.6 KB, 204 views)
File Type: png RS10-THD20.png (10.4 KB, 201 views)
Attached Files
File Type: txt RS10-MILLER.CIR.TXT (104.3 KB, 15 views)
File Type: txt RS10.CIR.TXT (103.1 KB, 15 views)
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Old 19th November 2011, 04:40 PM   #374
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Default Vertical MOSFET driver

And here is the driver for higher threshold fets (2SK1530/2SJ201).
Also included a THD20 plot + residual. This one is much smoother, because the weak inversion (sub-threshold) is also modeled (BSIM3.3)

Driver components that has been changed (value and/or position):
C23, R44, R45, Q29, Q30, Q31 & D21. All you need for the PCB mod are two jumpers and eight extra holes.

Cheers,
E
Attached Images
File Type: png RS10-Vert-OPS.png (28.2 KB, 165 views)
File Type: png RS10-Vert-THD20.png (9.1 KB, 90 views)
Attached Files
File Type: txt RS10-Vert.CIR.TXT (108.5 KB, 12 views)
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Old 19th November 2011, 06:17 PM   #375
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Hi Edmond,
Before I read your latest postings.
Here are te results for the 2SK1058 Vgs testing (just on 1 device) :
0,4V -> 35mA
0,7V -> 70mA
0,8V -> 100mA
0,9V -> 130mA
0,946V -> 150mA
1V -> 172mA
1,5V -> 400mA

I connected 10V to the drain through a 10E resistor and through a ampère meter.
I used the 2nd PSU channel to set the Vgs voltage. I read the voltage of Vgs on a voltmeter parallel over the 2nd PSU. I think it is right to do it that way.

Now I still don't know what the Vt is since the current ramps down but there is no real abrupt 'fall to zero' value ... but you asked especially for Vgs @ 150mA. I gues MC does the rest to draw the curve?

OK Now I will go for my 2SJ162 device ...

Cheers

Olivier
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Old 19th November 2011, 06:45 PM   #376
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And here is the testresult for the 2SJ162

0,0V -> 7,4mA
0,3V -> 53mA
0,46V -> 90mA
0,68V -> 150mA
1,05V -> 261mA
1,59 -> 445mA

Then it ran a bit hot :-)

By the way I did not mention in the 2SK1058 post (because I didn't expect the 2SJ162 to run current with no Vgs applied) that the 2SK1058 does not conduct at Vgs=0 (it is completely off).

I gues this means Vt is really low for both channels P & N.

I hope these results are useful for you ...

Now I go read your latest postings...

Cheers

Olivier
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Old 19th November 2011, 07:23 PM   #377
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Edmond,
Just another question.
While measuring the output of the amplifier with input connected to generator but no signal applied. What is the highest Vpp of output rubble one can tolerate?
Right now I still have 2mV on the output of my OPS. There is a 50Hz component and also really noise. Is this good? Bad?
Maybe interesting to say : actually there is no input filtering at all.

Another strange thing I noticed while testing. On a 100KHz squarewave the rising and falling slope are visually identical. However the top slope nicely curves towards a flat line at 200V/us. On the down side idem but there seems to be a tiny little overshoot. But it does not look like ringing (no no) I will take a picture tomorrow.

Cheers

Olivier
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Old 19th November 2011, 08:45 PM   #378
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Default Laterals

Hi Olivier,

Thanks for measuring the fets. I will incorporate your figures into the models.
As for the noise and hum, please let me think about it.
As for the tiny little overshoot, please, accept we don't live in a perfect world.
BTW, testing with a 100KHz square wave is an extreme torture (kind of waterboarding). Not every OPS will survive this.

Cheers,
E.
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Old 20th November 2011, 10:55 AM   #379
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Default noise

Quote:
Originally Posted by Olivier73 View Post
Edmond,
Just another question.
While measuring the output of the amplifier with input connected to generator but no signal applied. What is the highest Vpp of output rubble one can tolerate?
Right now I still have 2mV on the output of my OPS. There is a 50Hz component and also really noise. Is this good? Bad?
..........
Cheers
Olivier
Hi Olivier,

The noise level also depends on the bandwidth (of course). Below you see a sim of the output noise as function of BW. Up to 1MHz the noise is 167uV RMS. The peak to peak value is of course much higher, at least three times, depending on the crest value.
Also have a look at the output of one of my own amps. The noise is mainly dominated by HF ingress (Y=2mV/div, X=0.5us/div, BW=1MHz).
Hope this helps.

Cheers,
E.
Attached Images
File Type: png RS10 output noise.png (10.0 KB, 43 views)
File Type: jpg NAD-Noise.jpg (251.6 KB, 36 views)
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Old 20th November 2011, 11:15 AM   #380
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Default Pictures

Hi Edmond,

I am still not through your last postings about the OPS.

One thing on your schematic for the Front End : you changed the value of R16 & R17 to 100 Ohms. On the PCB actually they are bridged 0 ohms. I did that because I had oscillations on that node (both). However they were 1K resistors. Is 100E the best inbetween? How can this resistor cause oscillations anyway? It's a base resistor for the regulator Q, nothing more.

Hereby some pictures of the actual situation.

First the PCB itself. You can use it to see what components are in place, not placed and what components are placed on the fly (temporary placemnt). You see the simple millercaps flying there, bridging from R43 to R36 and R44 to R37. You can also see the different ground nodes (Signal Ground (the one on the full left upper screw), the feedback ground (top screw, middle terminalblock), the commonground (CGND see silkscreen), Decoupling Ground (middle screw, right terminalblock, green wire). As you notice very few capacitors are installed : only input DC blocking caps (C2A & C2B), 1 pair of decoupling caps C3 & C4 (the larger decoupling electrolyts are not installed C11 & C10), The lead-lag caps C12/13, the CMCL caps C15/16, and finally C8 the small cap across the Feedback cap C7 which is also installed). Not installed are : The right hand side decoupling caps (electrolyt C26/27 + polyprops C24/25) as stated before the left hand side decoupling electrolyt caps C10/11, the bias filter cap CB, the cascode zener voltage ref filter caps C22/23, the TMC caps C18->21), C17A&B (added at the last moment they are for stability but don't know how yet), C5/6 the stability caps at the right leg of the diff amps. Also C9/R19 feedforward is not installed. Also different protection components are not installed (diodes, resistors). The only protection installed are the VAS current limiter Q's.
Long story but hopefully means something to you.

Other pictures are :
100KHz sine response
100KHz square response (the bottom overshoot is difficult to see but OK I read that is acceptable)
1MHz sine response
1MHz square response

You can see it is very near the ULGF -3dB point of the amplifier.
You can also see the square wave output is higher at 1MHz than the sine wave at 1MHz (why is that? output transitor input capacitance? diff amp capacitance?)
Also notice signal generator has some ringing on the square wave. Amp coops well with that I seem to believe. But is the generator supposed to do that? Bad generator or input of amplifier does this ?

One more thing about your OPS. Do you think Error Correction is on the order for this amplifier? (I hope it is not incorporated in your OPS yet as I would deserve a slap in the face ).

Cheers

Olivier
Attached Images
File Type: jpg 0P1050810.jpg (438.2 KB, 76 views)
File Type: jpg 0P1050795.jpg (272.9 KB, 69 views)
File Type: jpg 0P1050796.jpg (236.4 KB, 40 views)
File Type: jpg 0P1050798.jpg (268.7 KB, 34 views)
File Type: jpg 0P1050807.JPG (263.7 KB, 39 views)
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