HEEEELLLPPP : M. Randy Slone Mirror Image Topology Construction - Troubles

[LineSource]

Can a Start-up Relay that inserts a feedback resistor just during the power-up into each LTP to establish the bias current for the VAS stage be used? This Bias Relay would open after a few seconds to remove any sonic effects.

[Olivier73]

Hi Edmond,

First of all, good thing to proceed in this thread as it is not longer directly linked to Bob's book thread.
This is indeed the latest version of the schematic and pcb. It corresponds to the actual fabricated PCB. I have 3 copies (if you would be interested you can have one)
The OPS isn't even designed. Well there were some simulated attemps but since I struggled so much with the frontend I decided not to invest time in ops'es yet. This week-end I will do some more testing to see if this frontend is realy as solid as it seems. Then, the time has come for the OPS to be designed.
The railvoltage can be set at any voltage , however my goal is to achieve something like 250W into 8 ohms. Only my FET Vgd's are on the low side 160V (if I remember well - got only 6 of each so i can still switch to another device ...)
You also asked me the question if I would prefer stability for thd? Yes, part of the goal is to have a highly reliable and forgiving amp without going over 0.001% THD 20KHz 250W 8ohm BW till 10th harmonic. I don't know if this is possible.

Later on it needs multiple security circuitry which I would like to elaborate.

If you allow me some dreaming, I dream of an amplifier solid as a tank (power wise & reliability wise), with very very respectable thd+n, sober casing, and possibly a nice looking pcb design.

Back with my feet on the ground I will continue VAS testing and simulating the loop assessments. I also want to measue some parameters like 3dB roll-off points, phase lag, amplitude, maybe some other and compare them with the simulation. This should show how the real thing deviates from the simulation.

In my last pcb I had a serious problem of phase lag (see older posts) I think this time it's different.

I will also send a sketch of how my testlab is grounded and how the amp is wired to all that. It's now installed with best results (after trying and trying) but i believe it's rather luck and that the best solution on paper is not working as well in my case ... more about that later ...

Cheers,

Olivier

[Olivier73]

LineSource,
This type of circuit corresponds to Bob's method to tame the VAS fighting current issue. There are people here that can answer more accurately than me but I would say (cfr Bob's book) the helper Q helps eliminate or reduce Hfe difference between Q's. This help the VAS to fight less. The resistor across the IPS legs resolves the rest of the problem but in your case you will remove this resistor after startup? I suppose to get rid of its effect on loop gain? I guess you imagine this fighting issue is especialy there on the startup and that after settlement it can be removed. Like a starter in a neon lamp. I guess the circuit will still alter due to temperature effects and others.
Don't know if you tried yet : simulate your schematic. Remember the VAS current and change one of the Re resistors of the current mirror Q's by 1% up and 1% down. See what the VAS current does?
Cheers,
Olivier

[Edmond Stuart]

Hi Olivier,

> I have 3 copies (if you would be interested you can have one)

You better keep them yourself. A spare PCB is always handy (for testing purposes etc) and use the other two for your final version.

>You also asked me the question if I would prefer stability for thd? Yes, part of the goal is to have a highly reliable and forgiving amp without going over 0.001% THD 20KHz 250W 8ohm BW till 10th harmonic. I don't know if this is possible.

I think 0.001% THD 20KHz is feasible, but not at 250W with only three pairs of lateral MOSFETs. The PGP amp has them too and syn08 wasn't happy with it (see the PGP website). Also I think that 75V is too high for these devices. I wouldn't go beyond 60V.

In the meantime, I'm experiencing troubles with the MOSFET models: MC 9 and MC10 give different results for the Vgs @ Id=150mA & Vds=63V
I've tested three pair of models:
1. Yours (form Hitachi?)
2. From the MC9 library
3. From this forum ( (p)spice models 4 2sk1058 & 2sj162 )
Here are the results (Vgs in mV for N-channel respectively P-channel devices):

model  MC9: Vgs-N  Vgs-P |  MC10: Vgs-N  Vgs-P  
  1         +923   +250  |        +1186   -418
  2         +434    +26  |         +469   -373
  3         +524   -154  |         +527   -158

As you see, different and/or unrealistic results between MC9 and MC10. The only models that gave (almost) identical results are from this forum. So I'm inclined to use these ones. However, about -156mV for the 2SJ162 seems too low (err... I mean too high). To go any further with he sims I really need the correct Vgs as it might have a significant impact on the driver configuration (if Vgs-N - Vgs-P < 2*Vbe I need a different driver than in the case if Vgs-N - Vgs-P > 2*Vbe ).

So please would you be so kind to measure the real Vgs @ 150mA. No need to measure it at Vds= 63V. 10 Volts or so will do, otherwise the MOSFEts get too hot.

Cheers,
E.

[Olivier73]

Hi Edmond,
I simulated (MC9) the miller loop response according to your instructions. The components on the board show following simulation results : ULGF 32MHz with 85° phase margin. Gain margin is 22dB at 300MHz.
However in your picture the gain rolls of near lower frequencies whereas in mine it becomes flat at around 200KHz and less.
I will also try the same for the CMCL loop.

Tomorrow I will measure the Vgs of my fet devices.
But if you feel this devices are not suitable for me, I can change to another device ... I know you favor verticals right? That's also good for me, however laterals are very rugged.

Indeed the files cannot be opened within MC9.

About the rail voltage you are indeed right. 75V is limit limit. That might be an input to switch device.

About the amount of pcb's I have (3pcs) I will not use them in the final project as they are lacking things like : fusing, relays, the real ops or better no ops if front only (the ops is dummy and incorporated on this pcb). If the track layout is good i will keep most of it but it will be placed on a new board anyway.

I will come back to you tomorrow.

Cheers,

Olivier

[Olivier73]

Edmond,
I read about your PGP amp. The THD requirements you have there are 10 fold better than what I intend.
However the Q count in the PGP is really huge.
For my information, the principle or basic schematic of the PGP is far superior compared to the one I try to run? I ask this because I thought this amp is already very complicated. I mean the frontend (as the OPS is not designed yet)?
Cheers
Olivier

[Olivier73]

Edmond,
CMCL results (same circuit actual on the pcb) :
CMCL ULGF : 390KHz phase margin : 90 degrees
Gain margin 32dB at 30MHz

question : are one of the results of the cmcl and miller loop to be compared? I see the 0dB passage of the CMCL @ 30MHz which is near the ULGF of the miller loop ? Hazard or is there a link somehow?

Cheers

Olivier

[Edmond Stuart]

Originally Posted by Olivier73

Hi Edmond,
I simulated (MC9) the miller loop response according to your instructions. The components on the board show following simulation results : ULGF 32MHz with 85° phase margin. Gain margin is 22dB at 300MHz.
However in your picture the gain rolls of near lower frequencies whereas in mine it becomes flat at around 200KHz and less.

Hi Olivier,

Hmm... weird. Can you show a picture (and schematic)?

I will also try the same for the CMCL loop.
Tomorrow I will measure the Vgs of my fet devices.

Please.

But if you feel this devices are not suitable for me, I can change to another device ... I know you favor verticals right? That's also good for me, however laterals are very rugged.

Indeed, they are very rugged. So just keep them. Maybe you can get some more them, i.e. four pairs per OPS.

Indeed the files cannot be opened within MC9.

About the rail voltage you are indeed right. 75V is limit limit. That might be an input to switch device.

About the amount of pcb's I have (3pcs) I will not use them in the final project as they are lacking things like : fusing, relays, the real ops or better no ops if front only (the ops is dummy and incorporated on this pcb). If the track layout is good i will keep most of it but it will be placed on a new board anyway.

I will come back to you tomorrow.

Cheers,

Olivier

What's wrong with your current PCB for the front-end? You can use it in conjunction with a separate PCB for the OPS. Splitting the PCBs for the front-end and OPS is always a good idea, especially when this project is still in a experimental stage.
BUT ... if you are intending to design a new PCB for the front-end, there are a few things that might be refined (for instance a more stable current source for the LTPs and a two pole low pass filter at the input, etc, etc)

Cheers,
E.

[Edmond Stuart]

Originally Posted by Olivier73

Edmond,
I read about your PGP amp. The THD requirements you have there are 10 fold better than what I intend.
However the Q count in the PGP is really huge.
For my information, the principle or basic schematic of the PGP is far superior compared to the one I try to run? I ask this because I thought this amp is already very complicated. I mean the front end (as the OPS is not designed yet)?
Cheers
Olivier

Hi Olivier,

You are right, the Q count in the PGP amp is really huge, not to say it is a bit over-engineered. But syn08 wants to break the 1ppm barrier, so a designed an ultra low distortion front-end (THD20k ~= 50ppb !).
Around 1ppm or below, the wiring however is extreme critical. Without suitable THD and spectrum analyzers it's impossible to figure out the right layout (besides, you can't hear it anyways).

Cheers,
E.

[Edmond Stuart]

Originally Posted by Olivier73

Edmond,
CMCL results (same circuit actual on the pcb) :
CMCL ULGF : 390KHz phase margin : 90 degrees
Gain margin 32dB at 30MHz

question : are one of the results of the cmcl and miller loop to be compared? I see the 0dB passage of the CMCL @ 30MHz which is near the ULGF of the miller loop ? Hazard or is there a link somehow?

Cheers

Olivier

Hi Olivier,

It's just a coincidence. Essentially, these figures are totally unrelated to each other. On the other hand, the lead-lag compensation at the VAS input does have an effect on the the CMCL response.

Cheers,
E.