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Old 9th January 2011, 03:46 PM   #351
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Quote:
Originally Posted by Olivier73 View Post
Edmond,
[snip]
I removed QCC1 and QCC2 and placed a bridge between Collector and Emitter. The rest was left in place.
[snip]
Olivier
Hi Olivier,

Of course, that's the easiest way. But in case you would decide to delete the cacodes definitely, you better delete the other trannies, because of the heat sink, which you can't move. (and modify some other component values to limit the dissipation of Q101 and Q102, or have these trannies a heat sink as well?)

Cheers,
E.
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Old 9th January 2011, 04:04 PM   #352
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Default Cascode

Hi Edmond,

Yes I removed them the easy way just to see the behavior. Since I run on 50V rail only (for now) & the VAS Iq = 12mA the DC operating point dissipates 600mW which doesn't heat Q16 and Q15 too much working w/o Cascode. But anyway the Cascode is mounted back on the PCB.
Since I could not notice any difference...

Yes also Q101/Q102 has heatsinks (not really necessary).

I am trying to find schematic mods in MC9 to make the simulated response look like the real one. This could give me a hint on what's wrong ...
I think I got a pole way too low in freq which makes the phase drop too steeply. Then I got some zero's too making it go uo again followed by more poles making it dive again (these last poles are probably logic) ... it's the first pole together with those zero's that makes the difference ...

If you see any strange thing on the DC voltages as posted before please let me know ...

Greetz

Olivier
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Old 9th January 2011, 04:10 PM   #353
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>I noticed just two differences that attracted my attention. I guess the one between >zeners is not important but the one on the signal input looks weird.

If you mean ~130mV vs ~40mV, that's okay, even better!
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Old 9th January 2011, 05:08 PM   #354
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Edmond,
I meant the one where the input signal is attached. In the sim it shows 0V whereas in reality it measures -40mV.
Also the point between RFB3 & 4 shows -40mV whereas the sim shows -10p or ~0V.
But then again, if the source is removed it is very logical that these -40mV are measured since it is the same voltage as on the other side of RFB3 because this side is connected nowhere. With signalsource the simulator puts that node at 0V whereas in reality it remains -40mV... probably just a sim thinigy.

There is one thing I discovered. The CAP in the GFL is not 4700uF but 470uF ... I wouldn't be able to see the rest of the PCB if it were 4700uF :-)

But ... wat nu?

Olivier
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Old 11th January 2011, 12:49 PM   #355
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Quote:
Originally Posted by Olivier73 View Post
Edmond,
I meant the one where the input signal is attached. In the sim it shows 0V whereas in reality it measures -40mV.
Hi Olivier,

This Vi node (the right side of RFB4) to which it is connected (or should be connected to) in reality? to the signal generator, right? Perhaps there is a cap in series with the signal generator's output. So, just measure the DC voltage right at the output of the signal generator. If it's 0V, then indeed something is wrong with the PCB.

Quote:
Also the point between RFB3 & 4 shows -40mV whereas the sim shows -10p or ~0V.
But then again, if the source is removed it is very logical that these -40mV are measured since it is the same voltage as on the other side of RFB3 because this side is connected nowhere. With signalsource the simulator puts that node at 0V whereas in reality it remains -40mV... probably just a sim thinigy.

There is one thing I discovered. The CAP in the GFL is not 4700uF but 470uF ... I wouldn't be able to see the rest of the PCB if it were 4700uF :-)

But ... wat nu?

Olivier
>The CAP in the GFL is not 4700uF but 470uF
Never mind.

Cheers,
E.
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Last edited by Edmond Stuart; 11th January 2011 at 12:56 PM.
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Old 12th January 2011, 08:13 PM   #356
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Hi Edmond,

Where the signal generator is connected to the circuit, that is just to the right of RFB4, the DC analyses on simulation indicates 0VDC.

In reality however I measured about -43mVDC. Admitted this is not a big difference but it struck me because some other important nodevoltages also are around 40mV as you can see on the DC-Analyses chart of previous posts.

So you asked me to measure the output probe of the signal generator only. Well, when it is connected we read 40mV, when released from the circuit but keeping my voltmeter still on the output probe the 40mV starts to fall slowly like a discharging cap finally reaching 0VDC. In other words the DC voltage on the output probe of the signal generator is 0VDC. The point on the PCB itslef is 40mV ... so indeed it looks like the signal generator has an output cap in series with it ....

What can you figure out of this??

if it is of any use : Sig Gen = METRIX GX310.

Bye & Cheers

Olivier
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Old 24th April 2011, 04:04 PM   #357
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Red face Next onset

Hi,
Here the latest implementation of the schematic & pcb for the amp i desperately want to build. The last version (before this one I working but not as i would like)
Main differences :
- PCB density much higher , pcb size is 40% of previous area due to smaller components (why use 500mW resistors while they dissipate only 10mW?). Main resistor set = 1/8 W, some are 1/4 W and a few are 1/2 W like feedback resistors, ...)
- The old pcb had optional components like both TMC & TPC compensation were implemented, with or without VBE multiplier (here is none since there is no ops and it's just proto to conlude ips and vas), all these extra stuff lengthen the traces and chances for parasites increase
- the famous link trace between ips and vas is kept as short as i could (still long i find, but ok this should do)
-the board is now 2 layer instead of 4 layer. I played with copper planes etc but this time i keep it simple. maybe 4L in 1.55mm FR4 thickness makes them be close to eachother especially those seperated only by a prepreg (?) something 200um. Crossing V rails like +70V and -70V separated with 200um FR4 might be close to arcing no? If not, at least influence eachother a lot.

Have a look
Attached Files
File Type: pdf RNO_AMP_3_20110424A_PCB.pdf (41.8 KB, 94 views)
File Type: pdf RNO_AMP_3_20110424A_SCH.pdf (23.9 KB, 174 views)
File Type: pdf RNO_AMP_3_20110424A_SSC.pdf (25.3 KB, 66 views)
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Old 4th May 2011, 09:24 PM   #358
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Hello there,

Here is the update of the schematic, (pcb will come later as i need to redraw it from scratch).

It contains both the cap between bases of the darlington vases and the rc network between rail and ouput-ips/input-vas node. Real testing will show which one helps best. C17A/C17B or C12-R25/R27-C13. Or both systems together.

I removed the fuses just to keep the test pcb small

I added a simple bias circuit and a tiny ops. beware that the .cir circuit uses 2SA1381 Q whereas i will use 2SA1930 Q for them with heatsinks (larger pcb , ... , too bad ).

I am still not sure about the baker clamps around the vas. I know Edmond changed to another circuit once but ... now i am unsure. Same thing for the cmcl circuit there are two options , this is the initial one.
Anyway, these options should work.

Notice C14 is optional idem for R19, C9, R36, R37, R44, R43.

More optionals than i wanted but ok, they are not causing tracks to become much longer.

I will create the pcb layout as small as possible. Will use 1.25mm tracks with 1.5mm spacing constraint.

Will be back l8er with more news

cheers

olivier
Attached Files
File Type: pdf RNO_AMP_4_20110430A.pdf (24.5 KB, 105 views)
File Type: txt RNO_AMP_4_20110430A.cir.txt (71.1 KB, 36 views)
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Old 6th September 2011, 10:01 PM   #359
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Hi,
Here a pdf version of my schematic and pcb version.
Feel free to comment...
Greetz,
Olivier
Attached Files
File Type: zip RNO_AMP_4_20110430A.zip (228.8 KB, 126 views)
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Old 16th November 2011, 01:42 PM   #360
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Quote:
Originally Posted by Olivier73 View Post
Hi,
Here a pdf version of my schematic and pcb version.
Feel free to comment...
Greetz,
Olivier
Hi Olivier,

Is this the latest version of the PCB?
BTW, please wait with modifying the front-end, as I have more in petto:
With a full fledged OPS the Miller loop behaves quite different.
Long story short story, no need to increase the time constants of the lead-lag compensation at the VAS input that much (330pf & 15 Ohms). 150pF & 33 Ohms will do just fine.

A few more questions: Did you already order the PCBs for the OPS, or are you still in the design phase?

Is the PSU voltage really that high: 75V?

Cheers,
E.
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