P3A Oscillation

[christian.lenci]

Hello everyone.

Since I always loved my stereo ESP P3A amp, I built an "upgraded" version of it. I made PCB for the two amps.

The schematic is attached. As you can see, I ugraded input transistors with 2SC1775s (high hfe, low noise), VAS transistor with a 2SA1406 (very low Cob), and got faster driver transistors (2SB649, 2SD669). I kept MJLs as output transistors as I got some samples from Onsemi for free.

I increased the capacitance of NFB and bootstrap caps (330uF instead of 100uF); I used Black Gates here. They aren't in the schematic but I also included 220uF bypass caps for the supply rails (Elna RJH, low ESR, equivalent to Pana FC). These are placed near output transistors; close to the input stage I bypassed the supply rails with two Wima MKP4 0.1uF caps.

All resistors are Holco H4.

I reduced C4 (Miller cap) to 68pF and provided feedforward compensation with a 10pF cap between VAS collector and negative LTP input.

I don't have a square wave generator. However, if I feed a sine wave into the amp, I have a small oscillation in the negative half of the wave. It starts when the signal approaches the negative peak, and it ceases when the signal crosses zero again. The positive half is clean. This happens for output signals greater than 4-5 Vpp, and only when the speaker is connected. With no speaker, the output is clean.

First thing I did was to remove feedforward compensation. Nothing changed. Then I tried to increase the miller cap. The ringing somewhat decreases but it is essentially the same for 82, 100 and 120 pF Miller caps. The oscillation is absolutely identical for the two amps.

So I tried to fit a 0.1uF cap across the two driver transistor bases. But now, while one amp is completely clean (also with 68pF miller and 10pF FF comp caps), in the other I have a strange peak (with noise) during the descending front of the negative half of the sine wave, starting from 3.5/4 kHz.

This is very strange to me, since the amps perform perfectly identical (oscillation and sound; most parts are matched) without this cap.

Any advice?

Thank you!

[jaycee]

IMO the CFP output stage is a nightmare....

You might find that you need some Miller capacitance on Q6

[Stormrider]

Why did you remove C6, 100pF from B to C of Q6?

[wahab]

Try to put a LR filter at the output , 1uH in paralel
with a 1R/3W non inductive resistor...
You can also reduce the transconductance of the differential
pair using two 47R or 100R resistors in serial with the
emitters of the 2SC1775. (Q1 and Q2)
This should tame down the oscillations...

[h_a]

VAS transistor with a 2SA1406 (very low Cob)

I reduced C4 (Miller cap) to 68pF

This reduces in both cases the Miller-capacitance, so you have a lot less phase/gain margin - means asking for stability problems.

If you don't have gear to test stability (especially into capacitive loads) I would go back to original values. Stick with the new transistor and increase C4 to the original value + the difference in Cob between original and new transistor.

Have fun, Hannes

[sakis]

10Pf cap doesnt show on the schematic ...also there is supposed to be a miller cap also nad the negative driver as other forum memebers indicated ...

usefull will be to have a picture of your pcb often things like that can be pcb related

[h_a]

pcb related

10pF can easily be pcb-related.

Reducing Miller-capacitance by using even lower Cob transistors and in addition a lower Miller-cap is asking for troubles. The orignal values were there for a reason.

Have fun, Hannes

[AKSA]

Agree with Hannes. You should not reduce the miller cap in this design. Further, the 100pF from C to B on Q6 is vital - this is, after all, the very side the instability occurs.

IMHO, a CFP is not well suited to Class AB. Class A - an entirely different matter.

I would suggest you try the Self EF Type II output stage, more stable, though less exotic. Then you should be able to actually reduce the miller cap, not before.

Hope this is helpful,

Hugh

[christian.lenci]

here are some updates:

I eliminated the feedforward compensation and increased the VAS miller cap to 220pF. The oscillation is still there.

With the original value for the miller cap (100pF) I tried to fit a 100pF across B and C of Q6. The oscillation was still there, and maybe was a little worse than without it.

I have no clue. Attached is the PCB layout.

[sakis]

to my opinion with this design of pcb you simply have no chance ..... traces down under C7 and C 3 are simply out of the question

also keep in mind that often electrolytics at this size in the signal path turn microphonic resulting to may unwanted situations

have you ever heard the term star ground ??? also current source at this distance will never work well ( needs to be as close is possible to the ltp )