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-   -   Class AB, Class AB Non-Switching, Class AB Soft Non-Switching (http://www.diyaudio.com/forums/solid-state/163220-class-ab-class-ab-non-switching-class-ab-soft-non-switching.html)

steph_tsf 15th March 2010 11:29 AM

Class AB, Class AB Non-Switching, Class AB Soft Non-Switching
 
3 Attachment(s)
hello,

attached you will find a .zip file containing three amplifiers, only differing in the vertical MOSFET output pair biasing arrangement :

- Class AB,
- Class AB Non-Switching,
- Class AB Soft Non-Switching

The three files are Tina 7 Texas Instruments schematics ready for simulation.

1.
The Class AB arrangement is a fixed voltage Vbe multiplier, decoupled by a big capacitor in parallel, as usual.

2.
The Class AB Non-Switching arrangement samples the 0,47 ohm source resistor voltage drop of both MOSFETs, individually, and compares the voltage drop with a reference voltage. When the 0,47 ohm resistor voltage drop is less than the reference voltage, the non-switching arrangement sends a correction current into the base of the Vbe multiplier that's associated to the MOSFET. Both MOSFETs thus never go off. However cumbersome or complicated it sounds, it works on paper (on simulation).

3.
The Class AB Soft Non-Switching arangement bias servo-loop is now getting a variable loop gain. The loop gain is minimized when the instantaneous 0,47 ohm current is minimal. The trick is in the differential amplifier operating current. It is now variable so the dynamic Rbe varies accordingly (log relation), and come in series with the 180 ohm emitter resistors. The 180 ohm resistors define the maximal loop gain, when the dynamic Rbe become small in front of 180 ohm.
The waveforms look perfect with a 1KHz 500 mV signal at the input. There are no hard corners nor inflexions anymore in the MOSFETs source currents. All the edges are nicely softened. When viewed from a certain distance, this may be confused with smooth genuine Class-A operation.

***

However, inputting a 500mV 10 KHz sinus signal enables us to see that :

- The Class AB arrangement delivers the cleanest MOSFETs source currents in the changeover zone, but the current drops to zero, and there are hard corners in the changeover zone, meaning a strong high-frequency harmonic content, internally. That's not new. This is known from long, and is the specificity (and flip side) of Class AB operation.

- The Class AB Non-Switching arrangement manages to keep both MOSFETs in conduction, but is prone to HF micro-oscillations bursts (1 Mhz, 2 S duration, 25 millivolts amplitude), very localized inside the changeover zone. Apart from the HF bursts, there are hard corners in the changeover zone, meaning a strong high-frequency harmonic content, internally.

- The Class AB Soft Non-Switching arrangement manages to keep both MOSFETs in conduction, and is delivering smooth rounded current edges, without harsh harmonic content. When looking closely, one can see that the Soft Non-Switching arrangement is perfectly working on the leading edges, when the MOSFETs currents go from low quiecent current to high load current. However, both MOSFETs do experience a small 5 s duration, 10 millivolts ampitude glitch at each trailing edge, when the MOSFETs currents need to go from high load current to low quiecent current.

Any suggestion welcome,
Steph

jan.didden 15th March 2010 11:38 AM

Hi Steph,

Not having Tina, I can't sim your circuit, but I looked at all your attachments.
A question: the figure titled "Sansui Diamond-Differential with current mirror loads and self biased VAS cascodes and Soft Non-Switching bias for IRF vertical MOSFETs_(10 KHz waves zoom" seems to show a cut-off of the output stage, although the titles says \'soft non-switching\'. Do I misunderstand something?

jd

steph_tsf 15th March 2010 11:53 AM

to janneman

1.
Please edit you post, and cancel most of the text you can see between QUOTE and /QUOTE. Thanks.
Seems you have not completely read my post : "However, both MOSFETs do experience a small 5 s duration, 10 millivolts ampitude glitch at each trailing edge, when the MOSFETs currents need to go from high load current to low quiecent current." Do you know what is a glitch ? Do you want to know how the glitch evolves when asking less power at the output ?

2.
Don\'t you understand that this particular thread is based on Tina 7 Texas Instruments schematics and simulations ? If you don\'t make the effort getting on Tina and running the simulations, what info are you providing to the communauty ?

3.
I\'ll answer all specific questions. PLEASE download Tina 7 Texas Instruments, open the schematics and run a few simulations.

4.
PLEASE edit your post as explained in 1. You need to do it within 20 minutes, otherwise the edit facility will be gone.

tinitus 15th March 2010 02:39 PM

Guys, no more of this getting personal :nownow: it will be infraction points from now on
stay on topic, please:cop:

Thread is cleaned up
Try again

Cal Weldon 15th March 2010 03:39 PM

Thread closed See here:

http://www.diyaudio.com/forums/solid...switching.html


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