I found the concept behind Visch's circuit interesting, but the physical implementation unusable.
Here is the boring version, based on the same PWM Iq control, but rationalized, without the awkwardness, the auxiliary supply, the dynamic problems, etc.
Revisch1 shows that when R7/R8/R10 are properly choosen and balanced, there is practically no variation between the no signal condition and 20Vpk output: the current in Q8, the servo transistor changes less than 1µA.
Under those conditions, the distortion is 0.025%.
It swings to within 1.5V of the supply rails: Revisch2. The Iq is 50mA, almost stable with the dynamic conditions.
This is a purely intellectual exercise, based on simulation only, but it indicates the topology might be usable after all.
Here is the boring version, based on the same PWM Iq control, but rationalized, without the awkwardness, the auxiliary supply, the dynamic problems, etc.
Revisch1 shows that when R7/R8/R10 are properly choosen and balanced, there is practically no variation between the no signal condition and 20Vpk output: the current in Q8, the servo transistor changes less than 1µA.
Under those conditions, the distortion is 0.025%.
It swings to within 1.5V of the supply rails: Revisch2. The Iq is 50mA, almost stable with the dynamic conditions.
This is a purely intellectual exercise, based on simulation only, but it indicates the topology might be usable after all.
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OK, I see JLH with 330R shunts from base to emitter, so this follower phase
splitter is behaving more like a folded concertina (either side of the rush).
I mean, you are burning more current in the 330R's than into the bases of
the output Siziklais. So its driving in a voltage mode, not current like JLH.
Which is a good thing... So far looking good.
Beyond that, whats news here? I see you got a pretty harsh B crossing.
Yet your phase margin looks way better than any of mine with similar
topology. Are you simming the phase margin on the dead spot perhaps?
splitter is behaving more like a folded concertina (either side of the rush).
I mean, you are burning more current in the 330R's than into the bases of
the output Siziklais. So its driving in a voltage mode, not current like JLH.
Which is a good thing... So far looking good.
Beyond that, whats news here? I see you got a pretty harsh B crossing.
Yet your phase margin looks way better than any of mine with similar
topology. Are you simming the phase margin on the dead spot perhaps?
This was the circuit I was referencing in my comments.
We got very similar drive, maybe for very different reasons?
I was trying to force a smooth AB (or even Hyper A) crossing.
I favor this arrangement of schottkys to shape an AB crossing.
Though no reason it couldn't be biased more heavily into B.
And again the question, can you trust the phase margin if its
computed upon the class B dead spot? We need some small
AB bias flowing if we are to know anything, right?
We got very similar drive, maybe for very different reasons?
I was trying to force a smooth AB (or even Hyper A) crossing.
I favor this arrangement of schottkys to shape an AB crossing.
Though no reason it couldn't be biased more heavily into B.
And again the question, can you trust the phase margin if its
computed upon the class B dead spot? We need some small
AB bias flowing if we are to know anything, right?
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The sole purpose of this circuit is to demonstrate the usability of the Visch principle, when applied properly.
It is therefore a class AB circuit, having a small (~50mA) quiescent, just for the transition: see Iq
It is simmed on the dead spot, but going into either of the active regions changes practically nothing: see Bode Pos and Neg, with + or - 3.5V output.
The servo has to be frozen by a voltage source, as the .ic don't work with Bode plot.
There is little to compare with your topology, except they both are circlo. This one is pure B, with a bare minimum of residual current.
Note: C3, R13 are not required, but they help symetrising the positive and negative slew rates. When they are present, SR is 150V/µs
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OK, this is probably the dumb question of the century:
But what exactly makes this circuit to be Visch or not?
Somehow I've missed the whole back story on Visch.
It just looks like folded concertina to me, is that Visch?
Or something more subtle going on that I've missed?
And while we are at it, what is CFP?
But what exactly makes this circuit to be Visch or not?
Somehow I've missed the whole back story on Visch.
It just looks like folded concertina to me, is that Visch?
Or something more subtle going on that I've missed?
And while we are at it, what is CFP?
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The Visch circuit was designed to control automatically the operation point in a class B push pull, without emitter resistors, adjustments or thermal feedback. But in its original implementation, the circuit had serious drawbacks, as we have seen in the other thread.
I reused the same fundamental idea, but in a totally different manner.
The CFP is the mixed-sex version of the darlington.
The Visch principle could be used on other topologies, but it is specially interesting in a circlo topology, because a single current source supplies current to both halves of the push-pull.
I reused the same fundamental idea, but in a totally different manner.
The CFP is the mixed-sex version of the darlington.
The Visch principle could be used on other topologies, but it is specially interesting in a circlo topology, because a single current source supplies current to both halves of the push-pull.
Oh, I thought that was called Sziklai. What do letters "CFP" actually stand for?
Sziklai pair - Wikipedia, the free encyclopedia
In original Visch, 'm seeing bootstrapped concertina? As opposed to folded style
seen in both our recent drawings. One less cap to worry about. I'm not yet sure
how the single diode can set the proper near-zero bias for an aB crossing? I'll
probably have to play with this on the simulator.
"Circlo topolgy" is another mystery phrase to me. Makes me think of Circlotron,
which is something else entirely... I thought this topology was JLH (John Lindsey
Hood)? Which detail is it that makes it "circlo" instead?
Sziklai pair - Wikipedia, the free encyclopedia
In original Visch, 'm seeing bootstrapped concertina? As opposed to folded style
seen in both our recent drawings. One less cap to worry about. I'm not yet sure
how the single diode can set the proper near-zero bias for an aB crossing? I'll
probably have to play with this on the simulator.
"Circlo topolgy" is another mystery phrase to me. Makes me think of Circlotron,
which is something else entirely... I thought this topology was JLH (John Lindsey
Hood)? Which detail is it that makes it "circlo" instead?
I'm pretty indifferent to etymology; the important thing is to know what we're talking about.
CFP stands for Complementary Feedback Pair AKA Sziklai AKA... French must also have their own pet name for it, but I don't even know it, although french is supposed to be my first language.
And once again, concertina, circlo, must be the same thing: all N output, with a N driver/phase splitter for voltage gain, or a P type for unity gain.
Now the bootstrap in the Visch circuit is not really a bootstrap: it does nothing for voltage swing, it just holds the reference value needed to create the correct bias current.
The original circuit works by balancing the sum of the bias into the driver and the quiescent current in the output devices to the the 15mA provided by the auxiliary source. When the equilibrium is reached, the diode goes into high impedance.
But the circuit is not very elegant, and more importantly, it is upset by dynamic conditions: the base bias is not sufficient for full swing, and some time is required to charge the capacitor to the new condition, and when the condition is reached, the Iq is so high that it almost becomes class A.
The adaptation I made is to low pass the diode output, and compare it to a virtual reference such that the setting doesn't change between purely static conditions, or when a square wave with a duty cycle of 0.5 appears on the diode (large signal condition).
Even in the large signal condition, the average current (and thus the quiescent current) is still under control, because of a PWM effect.
The scheme is of course only applicable to signals whose DC content is zero, but this is the case with audio signals.
This is something you have to take care in the sims, because if the output dwells a long time at a non-zero value, it upsets the servo and gives erratic results (calculation of .op conditions for instance).
CFP stands for Complementary Feedback Pair AKA Sziklai AKA... French must also have their own pet name for it, but I don't even know it, although french is supposed to be my first language.
And once again, concertina, circlo, must be the same thing: all N output, with a N driver/phase splitter for voltage gain, or a P type for unity gain.
Now the bootstrap in the Visch circuit is not really a bootstrap: it does nothing for voltage swing, it just holds the reference value needed to create the correct bias current.
The original circuit works by balancing the sum of the bias into the driver and the quiescent current in the output devices to the the 15mA provided by the auxiliary source. When the equilibrium is reached, the diode goes into high impedance.
But the circuit is not very elegant, and more importantly, it is upset by dynamic conditions: the base bias is not sufficient for full swing, and some time is required to charge the capacitor to the new condition, and when the condition is reached, the Iq is so high that it almost becomes class A.
The adaptation I made is to low pass the diode output, and compare it to a virtual reference such that the setting doesn't change between purely static conditions, or when a square wave with a duty cycle of 0.5 appears on the diode (large signal condition).
Even in the large signal condition, the average current (and thus the quiescent current) is still under control, because of a PWM effect.
The scheme is of course only applicable to signals whose DC content is zero, but this is the case with audio signals.
This is something you have to take care in the sims, because if the output dwells a long time at a non-zero value, it upsets the servo and gives erratic results (calculation of .op conditions for instance).
It is possible to push the slew-rate even further, to 250V/µs: see HiSR (the positive SR is even higher).
The penalty is shoot-through currents exceeding 10A, this is due to the sluggishness of the 3055s.
A word of caution for potential builders: when the circuit is initially powered, C1 is completely uncharged, which means the quiescent current is maximum for the time it takes to reach the servoed voltage.
If this issue is not handled properly, it could cause serious problems, and even blow the output transistors.
The penalty is shoot-through currents exceeding 10A, this is due to the sluggishness of the 3055s.
A word of caution for potential builders: when the circuit is initially powered, C1 is completely uncharged, which means the quiescent current is maximum for the time it takes to reach the servoed voltage.
If this issue is not handled properly, it could cause serious problems, and even blow the output transistors.
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