MOSFET Amplifier IRFP240/IRFP9240

[nigelwright7557]

Originally Posted by steph_tsf

sorry, I made a typo
please read :

" To me, yes, without further investigation, my first appreciation is that this circuit may suffer from thermal runaway.You may then download the Audio C

With my IRFP240/9240 amps I tend to run as low a bias as possible, just enough to kill crossover distortion. A new one I built tonightwith single output pair is running on a bias current of 7mA and sounds great at all volumes.

[mlloyd1]

i don't recall the spec for the input capacitance for these particular mosfets, but i think the effective input capacitance is significantly reduced (i.e. less than 800pF per device) by the local negative feedback courtesy of the source follower configuration.


mlloyd1

Originally Posted by steph_tsf

hi apexaudio,
... like needing to push a lot of current into the 800 pF x 4 = 3200 pF MOSFETs gate capacitances ...

[wahab]

Originally Posted by mlloyd1

i don't recall the spec for the input capacitance for these particular mosfets, but i think the effective input capacitance is significantly reduced (i.e. less than 800pF per device) by the local negative feedback courtesy of the source follower configuration.


mlloyd1

Right on , mlloyd, they are more or less neutralized by the
source follower scheme, as it s a bootstrap, which in that
case is local POSITIVE feedback...

[apexaudio]

Thanks Steph,
Your post is a reson to share this circuit. I agree with your sugestion, but this is discounted prodact for DIY. This is next step for beginers after building Gainclones. Sorry I dont speak English, I hope you understand me?
Best Regards for all Diyers, make amplifiers for fun not for competition.

[kenpeter]

Originally Posted by mlloyd1

i don't recall the spec for the input capacitance for these particular mosfets, but i think the effective input capacitance is significantly reduced (i.e. less than 800pF per device) by the local negative feedback courtesy of the source follower configuration.


mlloyd1

But you aren't just driving "capacitance", the moving target...
You ARE driving Qg/Gm. Any change in channel current can
only come because of a change in gate to channel charge.
This change takes energy, even if you fudge away Farads.

[AUDIOMEN]

The amplifier MOSFET schematic at first look is very simple and original. But I am wondering, why this simple shematic don't find wide use in proffesional amplifiers. Obvious there exist some problem.

[apexaudio]

R20 100ohm NTC

[AUDIOMEN]

Dear Steph_tsf, thanks for sending us webpage of new ALFET MOSFETs. I'm visiting this page for the first time. My impression regerding difference toward 2SK/2SJ audio series is not so great.

The Mosfet have only higher dissipation. The all other characteristics are the same.

[kenpeter]

Originally Posted by CBS240

A cap between emitter of Q9 and emitter of Q10 provides AC coupling between the OPT gates and allows the negative driver to discharge the positive mosfet gates and vice versa.

It appears to me that Q11 and Q12 already perform this function?
Multiplying the gate capacitance of Q13 and Q17 to span the gap
between the driving Sziklai pairs. Perhaps even Gm of the MOSFET
source contributes to the gain of this capacitive multiplier? I would
expect this span voltage to actively hold a very stable threshold.

Then again, does cap multiplier also make the gate harder to drive
by exact same amount? I havn't really done the math on this one.
Probably depends wether gate threshold or capacitiance dominates
control of Q11/12? I think I've gone and confused myself now.

And then to digest that in context that MOSFET gate cares only
Coulombs in/out, any value of "capacitance" depends upon the
circuit. I'm beyond lost now, and not really helping the situation...

[krachkiste]

Q11 and Q12 are for limiting the output current, and are supposed to have no effect during normal operation at all.

According to the datasheet the C_gs of an IRFP240 is max 1.2nF.
But the V_gs is only changing about 0.5V while the output swings 75V. So the effective C_gs presented to the VAS is about 0.5/75*1n2=8pF and can therefore be neglected.

The relevant capacitance is the gate-drain capacitance C_gd. The datasheet sais C_gd < 300pF @ V_gs>10V (and almost disappears for higher V_gs) and C_gd_max=1250pF (@0V V_gs)

So it very much depends on the output voltage, wether the FET-capacitances are a limiting factor or not. But most of the time they should not be.