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Old 9th March 2010, 11:30 AM   #111
nikwal is offline nikwal  Sweden
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Quote:
The amplifier will burn. Before you do that have on mind that I already do that in the past. The only Mosfet at output stage which will not burn is form 2SK/2SJ audio series but if you look their characteristic carefully they have more common with transistors then with POWER MOSFETS.
Used irfp series for years, I know with poor design the current could run away with clipping but it's not at all hard to get rid of, test should be done at higher frequencies too..
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10mA ?! You don't think much of hifi do you.. look at the tranceconductance chart and then tell me why I should stay below ~0.3A in my amplifiers.
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Also I vote for simpler vas stage(base&emitter to diff amp?w. emitter resistor lower resistance) and separate emitter follower buffer, and vbe circuit, hell I could'nt even get away without it and I only have one pair of output transistors..
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Old 9th March 2010, 12:09 PM   #112
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Quote:
Originally Posted by kenpeter View Post
OK, now running 300mA output bias as Krachkiste suggested...
1KHz sine looks perfect, 22KHz a little ragged, 96KHz awful...

But add 100uF from emitter to emitter as has been previously
suggested, sines clean and crossing nice all the way to 96KHz.
At least in simulation its does, whatever that counts for...

I have not yet checked what effect that cap's pole might
have upon phase margin? The sim so far does not appear to
ring or oscillate with 100uF added cap, but thats not a real
thorough analysis...
Don't take the 300mA I mentioned too serious. It's a good bias, but I just added a zero to the resistance value as a quick estimation, and ended up with that bias. So use whatever bias you please.

The 100F don't affect the loop-gain and thus stability.

I simmed the loop gain f_t to 91kHz.
Phase margin is 105
Gain margin is 28dB

so, looks pretty rugged.

A little overcompensated for my taste, but serves the needs of the application.

I was a little surprised, that the THD for 1kHz@45Vp simulates to a good 90dB while having only 38dB of loop gain at that frequency.
Thumbs up on that!

Last edited by krachkiste; 9th March 2010 at 12:14 PM.
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Old 9th March 2010, 12:32 PM   #113
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THD 90db ???????? ........ I dont know about this, I just opened kenpeters LT file, distortion isnt good at all and its oscilating so cant comment on this at all for now.

Last edited by homemodder; 9th March 2010 at 12:37 PM. Reason: PS my mistake, forgot to bias the mosfets properly.
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Old 9th March 2010, 12:42 PM   #114
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Now that is interesting.
Under what conditions did you observe oscillation?
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Old 9th March 2010, 12:50 PM   #115
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Quote:
Originally Posted by krachkiste View Post
Now that is interesting.
Under what conditions did you observe oscillation?
I didnt make it in time to edit, but all is fine, I forgot to bias the outputs.

Im quite surprised at the performance too, not bad at all, its the high vas current, but with such a high vas current its of limited use putting a EF in there but Ill try and lower the vas current to see what difference it makes.
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Old 9th March 2010, 01:49 PM   #116
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Loading a differential input pair with resistors is a double waste :
- your open loop gain drops
- the wire that connects to the VAS base only can push fast current into it
- the VAS base only sees a weak short-circuit (the resistor load) when needing to turn-off the VAS
-> as a result the VAS is fast at turn-on, but much slower at turn-off

Loading a differential pair using a current mirror removes all defects :
- the open loop rises
- the wire that connects to the VAS base can push fast current into it
- the wire that connects to the VAS base can act as a short-circuit
-> as a result the VAS is fast both at turn-on and at turn-off

What's also improved when loading with a current mirror, is that in case of need, the full differential pair current is made avaible to the VAS. The VAS can thus operate in Class-AB, for a maximum output current that's far more than twice its own quiescient current.
If you have a differential pair current with total Iq = 3mA, in case of heavy differential input, this will translate into nearly 3mA entering the base of the VAS. If the VAS is equipped with a transistor providing a current gain of 100, one may thus expect an output current of nearly 300mA available to the output devices, being BJT, vertical MOSFETs or lateral MOSFETs.

But wait a minute. How do you define the VAS quiescent current ?
If you are designing an asymetric amp, then this is very easy : you load the VAS by a constant current source, and your VAS Iq gets thus firmy defined, rock-solid.
If you are designing a fully symetric amp like the one we are talking about (Apex H23), then we need to think twice.

There is the US patent number 20040085130 by Sifen Luo (filed 2002) entitled "Simple self-biased cascode amplifier circuit".
In this circuit, everything simplifies down for defining a VAS Iq that's completely independent from the differential pair Iq. And you get the benefits of the cascode for free !

See attached Tina 7 Texas Instruments file, ready for simulation.

With this inexpensive mod, one can really boost the Apex H23 specs. The slew-rate gets ten times better. And THD gets halved. All this with a VAS Iq equal to 5mA. Which means less than 1/2 watt dissipation in the cascode transistor. The VAS input transistor only dissipate 15mW, because of his constant Vce voltage drive equal to 3V.

This revisited Apex HV23 is now a kind of "Non Slewing Amp" arrangement, something Giovanni Stochino presented between 1995 and 1998 in Wireless-World (Electronics World). But Giovanni Stochino arrangement was much more complicated !

Have fun !
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Old 10th March 2010, 01:37 AM   #117
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A lot of extra parts, just to "self" bias those cascodes.
Have you considered using a JFET+BJT as a depletion mode compound?

What was your reasoning, that a cascode was needed there anyway?
You also didn't specify some transistors, especially in and around the
cascodes... What model would you expect TINA is using for default?

Last edited by kenpeter; 10th March 2010 at 01:45 AM.
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Old 10th March 2010, 08:49 AM   #118
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Quote:
Originally Posted by kenpeter View Post
A lot of extra parts, just to "self" bias those cascodes. Have you considered using a JFET+BJT as a depletion mode compound?
Can you skech a schematic ? Then we'll determine if your proposed VAS is compatible with full symmetry designs and current mirrors. The question is : does your VAS exhibit a rock-solid quiescent current, when fed from a current mirror ?

Quote:
Originally Posted by kenpeter View Post
What was your reasoning, that a cascode was needed there anyway ?
As explained above, the cascode comes from free. The only concern was to load the differential input pair with a current mirror (increased gain and turn-off speed), then determine what kind of VAS was compatible.

Quote:
Originally Posted by kenpeter View Post
You didn't specify some transistors, especially in and around the cascodes... What model would you expect TINA is using for default?
When sketching design ideas, a viable starting point is to use default, regular transistors. Later on, one may specify real-world transistors like less beta, more max Vce voltage and lower cut-off frequency. And see the overall performance degradation it causes. One of the advantages of the cascode, is that it allows you to retain a high beta high speed (but low max Vce) transistor at the input. The input transistor doesn't see the Vce excursion. It works at a nearly 3V constant Vce. For the cascode transistor, you need to select a transistor able to dissipate 1 watts (TO-126 ot TO-202 outline are fine), high max Vce (say 300V), with decent speed (Ft 60 MHz) and decent beta (about 50). We had BF871 (NPN) and BF872 (PNP). Don't know if there are better (and still cheap) substitutes nowadays. See attached datasheets.
Attached Files
File Type: pdf BF871.pdf (49.8 KB, 365 views)
File Type: pdf BF872.pdf (50.1 KB, 181 views)
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Old 10th March 2010, 09:25 AM   #119
wahab is offline wahab  Algeria
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Quote:
Originally Posted by steph_tsf View Post
. The input transistor doesn't see the Vce excursion. It works at a nearly 3V constant Vce. .
What is gained in a end is lost in the other end...
At 3V, the Cob has almost its maximum value, reducing
greatly the devices Ft...
To work on optimal condition, there must be at least 10V Vce..
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Old 10th March 2010, 09:35 AM   #120
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Quote:
Originally Posted by steph_tsf View Post
Can you skech a schematic ? Then we'll determine if your proposed VAS is compatible with full symmetry designs and current mirrors. The question is : does your VAS exhibit a rock-solid quiescent current, when fed from a current mirror ?

As explained above, the cascode comes from free. The only concern was to load the differential input pair with a current mirror (increased gain and turn-off speed), then determine what kind of VAS was compatible.

When sketching design ideas, a viable starting point is to use default, regular transistors. Later on, one may specify real-world transistors like less beta, more max Vce voltage and lower cut-off frequency. And see the overall performance degradation it causes. One of the advantages of the cascode, is that it allows you to retain a high beta high speed (but low max Vce) transistor at the input. The input transistor doesn't see the Vce excursion. It works at a nearly 3V constant Vce. For the cascode transistor, you need to select a transistor able to dissipate 1 watts (TO-126 ot TO-202 outline are fine), high max Vce (say 300V), with decent speed (Ft 60 MHz) and decent beta (about 50). We had BF871 (NPN) and BF872 (PNP). Don't know if there are better (and still cheap) substitutes nowadays. See attached datasheets.
Why would one want to retain high beta low voltage transistors if you can use high beta high voltage, very low noise and low cob devices which are easily obtained and far superior to BC models.

A important parameter for the cascode transistor is high beta so instead you should be using a higher voltage input transistor and a medium to high voltage cascode transistor but with emphises on high beta, preferable a super beta model.

The input transistor will then still be working at a fixed but higher Vce and if you look at the performance youll notice that the circuit performance is quite better this way. BF872 is not a good cascode transistor too low beta.

One can see what the different performances will be by changing the spice parameters on the models and then see the effect it has on the circuit performance, this way you can see what kind of transistors are more suitable for the purpose. Current mirrror transistors should also be of the super beta type.

Could you show schematic as a jpg image or other format that other users not having tina could see, Im interested in seeing this self biased cascoded.

Wahab is spot on regarding cob.

Last edited by homemodder; 10th March 2010 at 09:37 AM.
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