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Old 6th March 2010, 10:15 PM   #91
generg is offline generg  Germany
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Quote:
Originally Posted by event horizon View Post
If you had used Lateral Mosfets in the output stage then i guess you could get away with such a simple biasing scheme. Lateral Mosfets have a negative temperature coefficient so they'll tend to reduce quiescent current as they heat up.

IRFP240 & it's complement have a positive temp coefficient (until they are drawing many Amps of current) so they'll conduct more current as they heat up. There is no allowance for this in your circuit diagram, you'd need something similar to what is used in a transistorised output stage.

I might be wrong, but i don't think so
A negative temperature coefficient (NTC) occurs when the thermal conductivity of a material rises with increasing temperature

A positive temperature coefficient (PTC) refers to materials that experience an increase in electrical resistance when their temperature is raised.

so I see no problem.......
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Old 6th March 2010, 10:24 PM   #92
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Originally Posted by generg View Post
A negative temperature coefficient (NTC) occurs when the thermal conductivity of a material rises with increasing temperature

A positive temperature coefficient (PTC) refers to materials that experience an increase in electrical resistance when their temperature is raised.

so I see no problem.......
Try glueing the bias transistor to an output transistor and that works well.
Sometimes too well !

I run my amps with a household iron on the heatsink to test it upto 100 degrees for thermal runaway. As yet had no problems with IRFP240/9240.
I do tend to run a minimal bias tho. Less than 10mA seems to get rid of crossover distortion.
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Old 6th March 2010, 10:26 PM   #93
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Nigel, does that mean you running those mosfets without a vbe multiplier too???
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Old 6th March 2010, 10:29 PM   #94
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Originally Posted by homemodder View Post
Nigel, does that mean you running those mosfets without a vbe multiplier too???
I use a simple Vbe multiplier but one not mounted on the MOSFETs or heatsink.
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Old 6th March 2010, 10:36 PM   #95
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OK I was just checking if you were getting away without it, the only way I use these mosfets and I dislike using the IRF parts as the toshibas ae so much better is in triple configuration. This way I get away using a small signal transistor glued to the heatsink or the mosfet itself. I run 100ma bias through them, I really cant understand how you can get away with 10ma bias although Ive never tried either, I guess some more experimenting is needed.
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Old 6th March 2010, 10:42 PM   #96
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Originally Posted by homemodder View Post
OK I was just checking if you were getting away without it, the only way I use these mosfets and I dislike using the IRF parts as the toshibas ae so much better is in triple configuration. This way I get away using a small signal transistor glued to the heatsink or the mosfet itself. I run 100ma bias through them, I really cant understand how you can get away with 10ma bias although Ive never tried either, I guess some more experimenting is needed.
I apply a 1 volt sine wave to the input, connect a speaker then slowly wind up the bias current until crossover distortion goes. The crossover distortion is really bad to start with but quickly goes around the 10mA mark.
The 10mA or less I usually get is for one pair of output transistors.

I found a good way of testing bias circuits was to heat up the heatsink with a household iron upto about 100 degrees and look for thermal runaway while monitoring the bias current.
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Old 6th March 2010, 10:59 PM   #97
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Originally Posted by nigelwright7557 View Post
I apply a 1 volt sine wave to the input, connect a speaker then slowly wind up the bias current until crossover distortion goes. The crossover distortion is really bad to start with but quickly goes around the 10mA mark.
The 10mA or less I usually get is for one pair of output transistors.

I found a good way of testing bias circuits was to heat up the heatsink with a household iron upto about 100 degrees and look for thermal runaway while monitoring the bias current.
How is overall distortion figures say into 20Khz.

This is the configuration I use with V mosfets, anything else just doesnt sound good to me. Without proper drive these V mosfets seem to have a lack of low down bass compaired to BJTS.
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Old 6th March 2010, 11:02 PM   #98
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Originally Posted by homemodder View Post
How is overall distortion figures say into 20Khz.

This is the configuration I use with V mosfets, anything else just doesnt sound good to me. Without proper drive these V mosfets seem to have a lack of low down bass compaired to BJTS.
It looks OK on the scope.
It sounds fine too which is the deciding factor for me.
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Old 7th March 2010, 12:30 AM   #99
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The conclusion form respect Mr. T.Leach that mosfet is not suitable for output audio stages are true.


Whatever
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Old 7th March 2010, 01:50 PM   #100
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Originally Posted by krachkiste View Post
But I would only rely on an actual measurement, or maybe on a spice simulation, if properly conducted.
I just ran a couple of Spice simulations using Tina 7 Texas Instruments. The result came as a surprise to me. It is possible to get a fast amp and still delivering low THD using a cascoded J-FET input stage biased at 1.25 mA in each FET, feeding a cascoded VAS biased at 25 mA without a complementary Darlington arrangement (thus, no more a Sziklai pair) and without emitter followers.

So, using a simple circuit, we get a 700 KHz -3dB corner frequency and a slew-rate (dV/dt) of about 150 V/s.

So yes, like krachkiste wrote, it definitely proves that the effective C_gs seen by the VAS is heavily divided by the Gm (combined to R_load) provided by the MOSFET. C_gs gets divided by something like between 20 to 100, depending on the load.

Moreover, putting MOSFETs in parallel doesn't impact dV/dt. On one side, you multiply the C_gs capacitance, but on the other side, you also multiply the Gm factor.

Attached you will find a schematic for such fast & low THD amp, edited under Tina 7 Texas Instruments, ready for simulation.

Please note the VAS emitter decoupling network.

You can download Tina 7 Texas Instruments free of charge here SPICE-Based Analog Simulation Program - TINA-TI - TI Tool Folder

Just one thin doubt : the MOSFET simulation model doesn't take into account possible dependencies of C_gs in function of I_d. It means that the simulation is maybe valid regarding dV/dt, but less valid regarding THD.

Quote:
Originally Posted by krachkiste View Post
And actually this whole discussion is one of the reasons (maybe there are more, I don't know yet) I will use an emitter follower driver stage before my FETs
According to this simulation, the last thing to do would be to add an emitter follower stage between the VAS and the MOSFETs. Can you explain again why you want to add an emitter follower stage ?
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