Low-distortion Super-pair Buffer simulation schematics - diyAudio
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Old 7th January 2010, 09:22 AM   #1
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Default Low-distortion Super-pair Buffer simulation schematics

This has probably already been investigated earlier, but I took a fresh look at a low-distortion voltage-follower/buffer, with encouraging results. The main idea is to use a super-pair (or half a diamond buffer) with a PNP driving an NPN (or vice versa), with identical currents through both, in order to cancel the Vbe compressive distortion. A current mirror is employed to equalize the currents through both voltage followers (the mechanical analogue to this idea dates back more than 300 years, to the Harrison chronometer and its bimetallic pendulum.)

I'm using the 2sc2705/2sa1145 pair in these example LTSpice simulations, but a wide variety of small-signal transistors give similar results. In this example, the small-signal (100mV amplitude) output FFT shows H2 down around -100 dB.
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File Type: jpg ef2_npn_cm_superpair.jpg (76.8 KB, 1912 views)
File Type: jpg ef2_npn_cm_superpair_100mv_fft.jpg (146.9 KB, 1809 views)

Last edited by linuxguru; 7th January 2010 at 09:40 AM. Reason: Added images; corrected typos
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Old 7th January 2010, 09:31 AM   #2
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A small transformation to the previous schematic (swap T1 and T3, flip the current mirror and load) yields the following schematic.

THD20 is even lower, mainly because the rearrangement of the load resistor R2 allows the entire incremental current through R2 || RL to be be mirrored and corrected (unlike the previous circuit).
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File Type: jpg ef2_pnp_cm_superpair.jpg (76.6 KB, 1658 views)
File Type: jpg ef2_pnp_cm_superpair_100mv_fft.jpg (144.2 KB, 1569 views)

Last edited by linuxguru; 7th January 2010 at 09:42 AM.
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Old 7th January 2010, 09:39 AM   #3
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The previous circuit is already very good, but a further significant improvement is possible. Consider the collector current in the first (NPN) follower - it is very close to the emitter current in the output (PNP) follower. It can simply be diverted into the load as shown below; this halves the operating current of both followers. More importantly, it also removes the Vce variation on Ic (Early effect) from the first follower.

Net effect: H2 almost vanishes at around -130..140 dB, as shown below.

Further improvements are possible, for instance thorugh the use of a Wilson current-mirror in place of the stock 2-BJT current-mirror shown. However, it's likely that any further returns will be diminishing.
Attached Images
File Type: jpg ef2_pnp_cm_superpair2.jpg (76.3 KB, 1517 views)
File Type: jpg ef2_pnp_cm_superpair2_100mv_fft.jpg (144.9 KB, 525 views)

Last edited by linuxguru; 7th January 2010 at 09:45 AM. Reason: Addendum
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Old 7th January 2010, 10:43 AM   #4
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What are the chances that a real world implementation will be -210dB down?

And, have you tried to look at the FFT of a two tone IM source and compare the the implementations - not sure that it works right in sims, but maybe it will show something of interest?

It looks too clean to be true, just guessing.

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Old 7th January 2010, 10:49 AM   #5
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This is a clear case when simulations not will meet reality. Sorry... but it could be worth investigating.
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Old 7th January 2010, 11:42 AM   #6
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H2 is around -135 dB, not -210 dB. That's within reach of the top-end opamps today, even for large-signal unity-gain buffers, so I see no reason why a 4-BJT circuit can't achieve -135 dB for small signals (~100 mV amplitude). The Wilson Current Mirror reached close to this level (for currents, not voltages) about ~50 years ago, using only 3 BJTs.

IMD simulations on LTspice are possible, but will require a large number of cycles to complete - at least 380 cycles for a 19 kHz + 20 kHz transient response simulation. It can be done with a bit of patience - however, in this case it probably will not yield any significant insight above what is already available with a single sinusoidal transient response simulation.

If the transistors are from the same batch and hand-matched for beta fairly closely, a physical implementation of this circuit will yield results that are within +/- 20 dB of the simulated numbers. It's only a simple 2-stage voltage follower, nothing exotic or special.
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Old 7th January 2010, 03:01 PM   #7
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Hi linuxguru,

That looks very interesting. Perhaps it would be a good buffer for between my CD player and power amplifier?

However I do not know too much about solid state (because I use tubes mostly!), so I would like to ask:

1.
How to bias the first transistor? (Is that a 5.3 V DC bias offset in the simulator?)

2.
As there are three NPN and one PNP transistors, might this lead to temperature related issues?

3.
How to calculate the output impedance of circuit 3?

4.
Which transistor types would be used for a 2V RMS signal, and what is the likely performance?

5.
Does the performance suffer when fed from a higher source impedance (say 2.5K to represent a 10K potentiometer at mid point)?


I feel as if I have asked too many questions?!?
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Old 7th January 2010, 03:28 PM   #8
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Quote:
Originally Posted by Gordy View Post
1. How to bias the first transistor? (Is that a 5.3 V DC bias offset in the simulator?)
That was just a simulation schematic, mainly for the purpose of showing its design goals/principles in an uncluttered manner. It is a building block, much like the Wilson Current Mirror, and needs additional circuitry to make it useful. I have a Headphone Amp in the early stages of design, using this buffer as the output stage, which I'll post later.

To bias it, you can simply use a resistive divider between Vcc and Ground. A small input DC blocking capacitor to the base will complete the input side. That 5.3V is not important - I used it mainly to get 6V across R2 in the first schematic, which sets a bias current of 2.5 mA for all the transistors.

Quote:
2. As there are three NPN and one PNP transistors, might this lead to temperature related issues?
Hmm - not unless they're mismatched, which of course can happen in the real world. In practice, one would mount Q1 and Q3 in close thermal contact, and similarly for Q2 and Q4.

Quote:
3. How to calculate the output impedance of circuit 3?
It can be analysed with a bit of sweat and tears using the AC small-signal Hybrid parameters of the two transistors, but that's overkill here. You can get a first-order simulation approximation by grounding the input, injecting a small voltage signal at the output and measuring the current swing in LTSpice.

Quote:
4. Which transistor types would be used for a 2V RMS signal, and what is the likely performance?
It depends on what kind of impedance you plan to drive. If it's high impedance (say more than 1k), just about any small-signal complementary BJT pair will work. My current favourites are the Toshiba 2sa970/2sc2240, but bc550c/bc560c or 2sa1015/2sc1815 should all work fine, with performance in the same ballpark as shown.

Quote:
5. Does the performance suffer when fed from a higher source impedance (say 2.5K to represent a 10K potentiometer at mid point)?
Yes, it will. The most likely uses of this buffer will have an intervening op-amp on the input side for low-level signal handling and conditioning. The bigger problem is that there may well be instability when driven by a high-impedance source, which will have to be cured by appropriate compensation and degeneration (I omitted all those details in the simulation schematics, but they will be required in a real design).
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Old 7th January 2010, 03:48 PM   #9
Gordy is offline Gordy  United Kingdom
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linuxguru, many thanks for your comprehensive (and quick) reply. I have noted your comments, and will do some reading-up on the subject.
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Old 7th January 2010, 04:15 PM   #10
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The related reading will be Pioneer US patents ## 4420725, 4433305, 4540951.
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