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sigpl 27th December 2009 01:05 PM

Why am I getting a positive phase shift
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Hi, new at the forum taking up an old interest.
Spending my xmas holidays sorting a shoe box full of old circuit sketches.
Also, came across the TopSpice simulator which I downloaded and just for fun tried out on some of my old circuits.

This one I have problem with. Can't understand what is causing the positive phase shift making it an 25 Mhz oscillator. Don't mind the (missing) details, just look at the idea. Neither mind the component choise, it is what I had to play with in the demo version.

Q3 and Q4 is a standard diff amp. The load, Q6 and Q7 is a standard current mirror leaving ( / taking) its excess current into Q9 and further into Q10 for amplification. Since Q10 and Q11 share a current source, the R5 will create a voltage swing for the output, from the current swing in Q10.

jcx 27th December 2009 02:49 PM

is compensation one of the missing circuit details?

I really wouldn't expect that many cascaded gain stages to stable without explicit Cdom

also never start with .AC analysis - always demonstrate that a realistic operating point has been found with a .TRAN and "debug" based on .TRAN circuit values

sigpl 27th December 2009 03:00 PM

No, compensation is not one of the missing details.
The compensation would of course had made it if I just had the normal negative phase shift and making the gain hit unity before the phase hit -180 deg.

All biases are OK.

sregor 27th December 2009 04:44 PM

If you follow the signal through, the out put is inverted (180 degrees) from the non inverting input. the signal is inverted at the collector of q3, the non inverte4d at the collector of q9 and emitter of q10, then inverted at the output stages. Many ways to correct this - I would reverse the current mirror on the input. Also, as mentioned, no compensation.

sigpl 27th December 2009 05:07 PM

Thanks for your idea to reverse the current mirror, but sorry, the same result.

Compensating, yes, but how? Since my positive phase appears already at about 50kHz a compensation had to start at a redicously low frequency. So to really know where to compensate, my question "why" is still valid.

There are of course plenty other methods to create the voltage swing, but this caught my interest since it gives a really nice transient answer, due to the current controlled current amplification.

godfrey 27th December 2009 06:46 PM

I don't know where the positive shift comes from, but maybe you can stabilize it with a capacitor between collector of Q11 and base of Q9 to set the dominant pole. Something like 100pF - maybe more.

There's huge open-loop gain in that circuit though, so it could be hard to tame.

Emitter resistors for Q3 and Q4 (say 100R each) would help a few things:
a) Better input-stage linearity.
b) Higher open-loop input impedance.
c) Allows you to reduce the compensation capacitor mentioned above at least 10-fold (maybe to 10pF), giving much better slew rate.

btw: Why are R11 and R12 mismatched?

Also: R11, R12 and R13 probably have nasty effects at HF. Reducing or getting rid of them might help.

To get a better idea of what's going on, try modeling it open-loop i.e. with the feedback disconnected.

sigpl 27th December 2009 08:03 PM

Thanks godfrey, the Q3, Q4 emitter resistors did the trick. Do you know why ? Always nice to learn the reasons behind. Maybe there wouldn't have been a problem if I had used a real current source (with limited input impedance) instead of the ideal one. I will test this to but then I have to use another SPICE copy. I have downloaded the LT Spice and it seems a lot better, allowing me to use zener diods too.

The R11 , R12 mismatch is due to the fact that a current mirror is not totally symmetric and the resistanse diff is needed to zero-bias the output. In reality there is a pot there to trim the output offset (typical solution).

As mentioned initially this was just a principal solution. Maybe I will use it in my upcoming MOSFET power amp project. I am testing out a few different solutions for each stage.

sigpl 27th December 2009 08:41 PM

Maybe I was a little to quick there. When adding the emitter restistances I got totally out of DC bias on output. When correcting this I am back with the positive feedback.

godfrey 27th December 2009 09:04 PM

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Originally Posted by sigpl (
The R11 , R12 mismatch is due to the fact that a current mirror is not totally symmetric and the resistance diff is needed to zero-bias the output. In reality there is a pot there to trim the output offset (typical solution).

The mirror's probably good enough. Most of the DC offset will be due to Q4's base current flowing through R14. If you use ac coupling e.g. as shown, then the voltage drops across the 39K resistors will match to some extent to improve DC offset. You need Q3 and Q4 to be fairly well matched, though.

Your 10mA LTP current looks quite high, especially with R14 = 39K. The voltage drop across R14 must be quite high - maybe a volt or so? Reducing the current and/or resistance would help the DC offset a lot. Remember even if you trim it right, it will drift with temperature.

I don't like the idea of trimming the mirror because that will change the gain as well, and also cause distortion - it's much better to adjust so Q3 and Q4 have equal collector currents. I included the 1K resistors as stupid-proofing in case the trimmer goes open-circuit.

The 100pF is not just for RF filtering. It's main job is to keep Q3's base at low impedance relative to earth at high frequencies, especially when nothing is connected at the input. Otherwise you risk oscillations again.

I'm off to the pub now for a quick one before closing time :cheers:
Will post about the HF stuff later (sobriety permitting) or tomorrow.

sigpl 27th December 2009 09:41 PM

Yes you are probably right about the mirror and the base current on Q4. The 10 mA was not intentional, just left there since earlier simulations. Changed down to 2 mA. But the positive phase is still there.

Thanks for your effort, have one beer for me too. I'm headed for the sofa watching snooker on Eurosport.

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